SLVSE94G September   2018  – June 2024

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Hot Plug-In and Inrush Current Control
        1. 8.3.1.1 Thermal Regulation Loop
      2. 8.3.2  PGOOD and PGTH
        1. 8.3.2.1 PGTH as VOUT Sensing Input
      3. 8.3.3  Undervoltage Lockout (UVLO)
      4. 8.3.4  Overvoltage Protection (OVP)
      5. 8.3.5  Input Reverse Polarity Protection (B_GATE, DRV)
      6. 8.3.6  Reverse Current Protection
      7. 8.3.7  Overload and Short-Circuit Protection
        1. 8.3.7.1 Overload Protection
          1. 8.3.7.1.1 Active Current Limiting at 1 × IOL (TPS26630 and TPS26632 Only)
          2. 8.3.7.1.2 Active Current Limiting With 2 × IOL Pulse Current Support (TPS26631, TPS26633, TPS26635, TPS26636, and TPS26637 Only)
        2. 8.3.7.2 Short-Circuit Protection
          1. 8.3.7.2.1 Start-Up With Short Circuit on Output
      8. 8.3.8  Output Power Limiting, PLIM (TPS26632, TPS26633, TPS26635, TPS26636, and TPS26637 Only)
      9. 8.3.9  Current Monitoring Output (IMON)
      10. 8.3.10 FAULT Response (FLT)
      11. 8.3.11 IN_SYS, IN, OUT, and GND Pins
      12. 8.3.12 Thermal Shutdown
      13. 8.3.13 Low Current Shutdown Control (SHDN)
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Power Path Protection in a PLC System
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Programming the Current-Limit Threshold—R(ILIM) Selection
        2. 9.2.2.2 Undervoltage Lockout and Overvoltage Set Point
        3. 9.2.2.3 Output Buffer Capacitor – COUT
        4. 9.2.2.4 PGTH Set Point
        5. 9.2.2.5 Setting Output Voltage Ramp Time—(tdVdT)
          1. 9.2.2.5.1 Support Component Selections— RPGOOD and C(IN)
        6. 9.2.2.6 Selecting Q1, Q2 and TVS Clamp for Surge Protection
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Simple 24-V Power Supply Path Protection
      2. 9.3.2 Priority Power MUX Operation
      3. 9.3.3 Input Protection for a Compact 24-V Auxiliary Power Supply for Servo Drives
    4. 9.4 Dos and Do Nots
    5. 9.5 Power Supply Recommendations
      1. 9.5.1 Transient Protection
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

TPS2663 TPS26630, TPS26631 RGE Package;24-Pin VQFN(Top View)Figure 5-1 TPS26630, TPS26631 RGE Package;24-Pin VQFN(Top View)
TPS2663 TPS26632, TPS26633, TPS26635, TPS26637 RGE Package;24-Pin VQFN(Top View)Figure 5-3 TPS26632, TPS26633, TPS26635, TPS26637 RGE Package;24-Pin VQFN(Top View)
TPS2663 TPS26631 PWP Package,20-Pin HTSSOP(Top View)Figure 5-2 TPS26631 PWP Package,20-Pin HTSSOP(Top View)
TPS2663 TPS26633, TPS26636, TPS26637 PWP Package;20-Pin HTSSOP(Top View)Figure 5-4 TPS26633, TPS26636, TPS26637 PWP Package;20-Pin HTSSOP(Top View)
Table 5-1 Pin Configuration and Functions
PIN TYPE(1) DESCRIPTION
NAME VQFN HTSSOP
IN 1 1 P Power input. Connects to the DRAIN of the internal FET.
2 2
— 3
B_GATE 3 4 O Blocking FET gate driver output. Connect B_GATE to GATE of the external NFET. If external FET is not used then leave B_GATE pin floating. See the Input Reverse Polarity Protection (B_GATE, DRV) section.
DRV 4 5 O Blocking FET fast pulldown switch drive. Connect DRV to the GATE of external pulldown switch. Leave this pin floating if external N-FET is not used.
IN_SYS 5 6 P Power input and supply voltage of the device. When an external Blocking FET is used then connect IN_SYS to source of the FET. Short IN_SYS to IN in case blocking FET is not used.
UVLO 6 7 I Input for setting the programmable undervoltage lockout threshold. An undervoltage event turns off the internal FET and asserts FLT to indicate the power-failure. Connect UVLO pin to GND pin to select the internal default threshold.
OVP 7 8 I Input for setting the programmable overvoltage protection threshold (For TPS26630 and TPS26631 Only). An overvoltage event turns off the internal FET and asserts FLT to indicate the overvoltage fault. Connect OVP pin to GND pin externally to select the internal default threshold.
PLIM 7 8 I Input for setting the programmable output power limiting threshold (For TPS26632, TPS26633, TPS26635,TPS26636 and TPS26637 Only). Connect a resistor across PLIM to GND to set the output power limit. Connect PLIM to GND if PLIM feature is not used. See the Output Power Limiting, PLIM (TPS26632, TPS26633, TPS26635 and TPS26636 Only) section.
GND 8 9 — Connect GND to system ground.
dVdT 9 10 I/O A capacitor from this pin to GND sets output voltage slew rate. See the Hot Plug-In and InRush Current Control section.
ILIM 10 11 I/O A resistor from this pin to GND sets the overload and short-circuit current limit. See the Overload and Short-Circuit Protection section.
MODE 11 12 I Mode selection pin for overload fault response. See the Device Functional Modes section.
SHDN 12 13 I Shutdown pin. Pulling SHDN low makes the device to enter into low power shutdown mode. Cycling SHDN pin voltage resets the device that has latched off due to a fault condition.
IMON 13 14 O Analog current monitor output. This pin sources a scaled down ratio of current through the internal FET. A resistor from this pin to GND converts current to proportional voltage. If unused, leave this pin floating.
FLT 14 15 O Fault event indicator. This pin is an open drain output. If unused, leave floating or connect to GND.
PGTH 15 16 I PGOOD comparator input.
PGOOD 16 17 O Active High. A high indicates PGTH has crossed the V(PGTHR) threshold and the internal FET is enhanced. PGOOD goes low when V(PGTH) hits V(PGTHF) threshold. If PGOOD is unused then connect to GND or leave it floating.
OUT 17 18 P Power output of the device.
18 19
— 20
N. C 19 — — No connect.
20
21
22
23
24
PowerPAD™
integrated circuit package		 — — — Connect PowerPAD integrated circuit package to GND plane for heat sinking. Do not use PowerPAD integrated circuit package as the only electrical connection to GND.
(1) I = input, O = output, I/O = input and output, P = power