SLVSE94G September   2018  – June 2024

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Hot Plug-In and Inrush Current Control
        1. 8.3.1.1 Thermal Regulation Loop
      2. 8.3.2  PGOOD and PGTH
        1. 8.3.2.1 PGTH as VOUT Sensing Input
      3. 8.3.3  Undervoltage Lockout (UVLO)
      4. 8.3.4  Overvoltage Protection (OVP)
      5. 8.3.5  Input Reverse Polarity Protection (B_GATE, DRV)
      6. 8.3.6  Reverse Current Protection
      7. 8.3.7  Overload and Short-Circuit Protection
        1. 8.3.7.1 Overload Protection
          1. 8.3.7.1.1 Active Current Limiting at 1 × IOL (TPS26630 and TPS26632 Only)
          2. 8.3.7.1.2 Active Current Limiting With 2 × IOL Pulse Current Support (TPS26631, TPS26633, TPS26635, TPS26636, and TPS26637 Only)
        2. 8.3.7.2 Short-Circuit Protection
          1. 8.3.7.2.1 Start-Up With Short Circuit on Output
      8. 8.3.8  Output Power Limiting, PLIM (TPS26632, TPS26633, TPS26635, TPS26636, and TPS26637 Only)
      9. 8.3.9  Current Monitoring Output (IMON)
      10. 8.3.10 FAULT Response (FLT)
      11. 8.3.11 IN_SYS, IN, OUT, and GND Pins
      12. 8.3.12 Thermal Shutdown
      13. 8.3.13 Low Current Shutdown Control (SHDN)
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Power Path Protection in a PLC System
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Programming the Current-Limit Threshold—R(ILIM) Selection
        2. 9.2.2.2 Undervoltage Lockout and Overvoltage Set Point
        3. 9.2.2.3 Output Buffer Capacitor – COUT
        4. 9.2.2.4 PGTH Set Point
        5. 9.2.2.5 Setting Output Voltage Ramp Time—(tdVdT)
          1. 9.2.2.5.1 Support Component Selections— RPGOOD and C(IN)
        6. 9.2.2.6 Selecting Q1, Q2 and TVS Clamp for Surge Protection
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Simple 24-V Power Supply Path Protection
      2. 9.3.2 Priority Power MUX Operation
      3. 9.3.3 Input Protection for a Compact 24-V Auxiliary Power Supply for Servo Drives
    4. 9.4 Dos and Do Nots
    5. 9.5 Power Supply Recommendations
      1. 9.5.1 Transient Protection
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.2.2.2 Undervoltage Lockout and Overvoltage Set Point

The undervoltage lockout (UVLO) and overvoltage trip point are adjusted using an external voltage divider network of R1, R2 and R3 connected between IN_SYS, UVLO, OVP and GND pins of the device. Use Equation 9 and Equation 10 to calculate the values required for setting the undervoltage and overvoltage.

Equation 9. TPS2663
Equation 10. TPS2663

For minimizing the input current drawn from the power supply {I(R123) = V(IN) / (R1 + R2 + R3)}, TI recommends to use higher value resistance for R1, R2 and R3.

However, the leakage current due to external active components connected at resistor string can add error to these calculations. So, the resistor string current, I(R123) must be chosen to be 20x greater than the leakage current of UVLO and OVP pins.

From the device electrical specifications, V(OVPR) = 1.2 V and V(UVLOR) = 1.2 V. From the design requirements, V(OV) is 33 V and V(UV) is 18 V. To solve the equation, first choose the value of R3 = 34 kΩ and use Equation 9 to solve for (R1 + R2) = 916 kΩ. Use Equation 10 and value of (R1 + R2) to solve for R2 = 29.4 kΩ, and finally R1= 887 kΩ.

Choose the closest standard 1% resistor values: R1 = 887 kΩ, R2 = 29.4 kΩ, and R3 = 34 kΩ.

The UVLO and the OVP pins can also be connected to the GND pin to enable the internal default V(OV) = 34.2 V and V(UV) = 15.6 V.