SLVSEO0A August   2021  – May 2022

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: DC Specifications
    6. 7.6  Electrical Characteristics: Power Consumption
    7. 7.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 7.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 7.9  Timing Requirements
    10. 7.10 Switching Characteristics
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs
        1. 8.3.1.1 Analog Input Protection
        2. 8.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 8.3.1.3 Analog Input Offset Adjust
      2. 8.3.2 ADC Core
        1. 8.3.2.1 ADC Theory of Operation
        2. 8.3.2.2 ADC Core Calibration
        3. 8.3.2.3 Analog Reference Voltage
        4. 8.3.2.4 ADC Overrange Detection
        5. 8.3.2.5 Code Error Rate (CER)
      3. 8.3.3 Temperature Monitoring Diode
      4. 8.3.4 Timestamp
      5. 8.3.5 Clocking
        1. 8.3.5.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 8.3.5.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 8.3.5.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 8.3.5.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 8.3.5.3.2 Automatic SYSREF Calibration
      6. 8.3.6 Programmable FIR Filter (PFIR)
        1. 8.3.6.1 Dual Channel Equalization
        2. 8.3.6.2 Single Channel Equalization
        3. 8.3.6.3 Time Varying Filter
      7. 8.3.7 Digital Down Converters (DDC)
        1. 8.3.7.1 Rounding and Saturation
        2. 8.3.7.2 Numerically-Controlled Oscillator and Complex Mixer
          1. 8.3.7.2.1 NCO Fast Frequency Hopping (FFH)
          2. 8.3.7.2.2 NCO Selection
          3. 8.3.7.2.3 Basic NCO Frequency Setting Mode
          4. 8.3.7.2.4 Rational NCO Frequency Setting Mode
          5. 8.3.7.2.5 NCO Phase Offset Setting
          6. 8.3.7.2.6 NCO Phase Synchronization
        3. 8.3.7.3 Decimation Filters
        4. 8.3.7.4 Output Data Format
        5. 8.3.7.5 Decimation Settings
          1. 8.3.7.5.1 Decimation Factor
          2. 8.3.7.5.2 DDC Gain Boost
      8. 8.3.8 JESD204C Interface
        1. 8.3.8.1  Transport Layer
        2. 8.3.8.2  Scrambler
        3. 8.3.8.3  Link Layer
        4. 8.3.8.4  8B/10B Link Layer
          1. 8.3.8.4.1 Data Encoding (8B/10B)
          2. 8.3.8.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 8.3.8.4.3 Code Group Synchronization (CGS)
          4. 8.3.8.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 8.3.8.4.5 Frame and Multiframe Monitoring
        5. 8.3.8.5  64B/66B Link Layer
          1. 8.3.8.5.1 64B/66B Encoding
          2. 8.3.8.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
          3. 8.3.8.5.3 Block, Multiblock and Extended Multiblock Alignment using Sync Header
            1. 8.3.8.5.3.1 Cyclic Redundancy Check (CRC) Mode
            2. 8.3.8.5.3.2 Forward Error Correction (FEC) Mode
          4. 8.3.8.5.4 Initial Lane Alignment
          5. 8.3.8.5.5 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 8.3.8.6  Physical Layer
        7. 8.3.8.7  SerDes Pre-Emphasis
        8. 8.3.8.8  JESD204C Enable
        9. 8.3.8.9  Multi-Device Synchronization and Deterministic Latency
        10. 8.3.8.10 Operation in Subclass 0 Systems
      9. 8.3.9 Alarm Monitoring
        1. 8.3.9.1 NCO Upset Detection
        2. 8.3.9.2 Clock Upset Detection
        3. 8.3.9.3 FIFO Upset Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Dual-Channel Mode
      2. 8.4.2 Single-Channel Mode (DES Mode)
      3. 8.4.3 Dual-Input Single-Channel Mode (DUAL DES Mode)
      4. 8.4.4 JESD204C Modes
        1. 8.4.4.1 JESD204C Operating Modes Table
        2. 8.4.4.2 JESD204C Modes continued
        3. 8.4.4.3 JESD204C Transport Layer Data Formats
        4. 8.4.4.4 64B/66B Sync Header Stream Configuration
        5. 8.4.4.5 Dual DDC and Redundant Data Mode
      5. 8.4.5 Power-Down Modes
      6. 8.4.6 Test Modes
        1. 8.4.6.1 Serializer Test-Mode Details
        2. 8.4.6.2 PRBS Test Modes
        3. 8.4.6.3 Clock Pattern Mode
        4. 8.4.6.4 Ramp Test Mode
        5. 8.4.6.5 Short and Long Transport Test Mode
          1. 8.4.6.5.1 Short Transport Test Pattern
          2. 8.4.6.5.2 Long Transport Test Pattern
        6. 8.4.6.6 D21.5 Test Mode
        7. 8.4.6.7 K28.5 Test Mode
        8. 8.4.6.8 Repeated ILA Test Mode
        9. 8.4.6.9 Modified RPAT Test Mode
      7. 8.4.7 Calibration Modes and Trimming
        1. 8.4.7.1 Foreground Calibration Mode
        2. 8.4.7.2 Background Calibration Mode
        3. 8.4.7.3 Low-Power Background Calibration (LPBG) Mode
      8. 8.4.8 Offset Calibration
      9. 8.4.9 Trimming
    5. 8.5 Programming
      1. 8.5.1 Using the Serial Interface
        1. 8.5.1.1 SCS
        2. 8.5.1.2 SCLK
        3. 8.5.1.3 SDI
        4. 8.5.1.4 SDO
        5. 8.5.1.5 Streaming Mode
    6. 8.6 SPI Register Map
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Wideband RF Sampling Receiver
        1. 9.2.1.1 Design Requirements
          1. 9.2.1.1.1 Input Signal Path
          2. 9.2.1.1.2 Clocking
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Calculating Values of AC-Coupling Capacitors
        3. 9.2.1.3 Application Curves
    3. 9.3 Initialization Set Up
  10. 10Power Supply Recommendations
    1. 10.1 Power Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 142
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

8.3.7.4 Output Data Format

The DDC output data consists of 15-bit complex data plus the two overrange threshold-detection control bits.Table 8-15 shows the data output format for the DDC modes.

Table 8-15 Complex Decimation Output Sample Format
I/Q
SAMPLE		16-BIT OUTPUT WORD
1514131211109876543210
IDDC in-phase (I) 15-bit output dataOVR_T0
QDDC quadrature (Q) 15-bit output dataOVR_T1