SLVU097B October   2003  – October 2021 TPS54350

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background
    2. 1.2 Performance Specification Summary
    3. 1.3 Modifications
      1. 1.3.1 Output Voltage Setpoint
      2. 1.3.2 Switching Frequency
      3. 1.3.3 Input Filter
      4. 1.3.4 UVLO Programming
      5. 1.3.5 Synchronization
      6. 1.3.6 Power Good
      7. 1.3.7 Synchronous Low-Side FET
      8. 1.3.8 Optional Output Filtering
  3. 2Test Setup and Results
    1. 2.1  Input/Output Connections
    2. 2.2  Efficiency
    3. 2.3  Power Dissipation
    4. 2.4  Output Voltage Regulation
    5. 2.5  Load Transients
    6. 2.6  Loop Characteristic
    7. 2.7  Output Voltage Ripple
    8. 2.8  Input Voltage Ripple
    9. 2.9  Gate Drive
    10. 2.10 Powering Up and Down
  4. 3Board Layout
    1. 3.1 Layout
  5. 4Schematic and Bill of Materials
    1. 4.1 Bill of Materials
  6. 5Revision History

Input/Output Connections

The TPS54350EVM−235 has the following two input/output connectors: VI(J1) and VO (J3). A diagram showing the connection points is shown in Figure 2-1. A power supply capable of supplying 5 A should be connected to J1 through a pair of 20 AWG wires. The load should be connected to J2 through a pair of 20 AWG wires. The maximum load current capability should be 3 A. Wire lengths should be minimized to reduce losses in the wires. Test point TP9 provides a place to easily connect an oscilloscope voltage probe to monitor the output voltage. The TPS54350 is intended to be used as a point of load regulator. In typical applications, it is usually located close to the input voltage source. When using the TPS54350EVM−235 with an external power supply as the source for VI, an additional bulk capacitor can be required, depending on the output impedance of the source and length of the hook-up wires. The test results presented are obtained using a 47-mF, 25-V additional input capacitor. Alternately, C1 can be populated with an input filter capacitor.

GUID-20210929-SS0I-PNJR-RFBN-FTK2FT7MJQH8-low.gif Figure 2-1 Connection Diagram