Figure 5-1 through Figure 5-5 show the board layout of the TPS54329EEVM-056. The top layer contains the main power traces for VIN, VO, and ground. Also on the top layer are connections for the pins of the TPS54329E and a large area filled with ground. Many of the signal traces also are located on the top side. The input decoupling capacitors are located as close to the IC as possible. The input and output connectors, test points, and all of the components are located on the top side. An analog ground (GND) area is provided on the top side. Analog ground (GND) and power ground (PGND) are connected at a single point on the top layer near C6. The two internal layers are completely dedicated to power ground planes. The bottom layer is primarily power ground. A copper pour area on the bottom layer is used to connect the switching node (SW) to the output inductor and the boost capacitor. Traces also connect the enable control jumper, EN, VREG5, and LOOP test points, and the feedback trace from VOUT to the voltage setpoint divider network.

Figure 5-1 Top Assembly

Figure 5-2 Top Layer

Figure 5-3 Internal Layer 1

Figure 5-4 Internal Layer 2

Figure 5-5 Bottom Layer