SLVUBM5A April   2019  – August 2021 TPS54A24

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background
    2. 1.2 Performance Characteristics Summary
    3. 1.3 Modifications
      1. 1.3.1 Output Voltage Setpoint
      2. 1.3.2 Adjustable UVLO
      3. 1.3.3 Component Values to Evaluate Common Output Voltages
  3. 2Test Setup and Results
    1. 2.1  Input/Output Connections
    2. 2.2  Efficiency
    3. 2.3  Output Voltage Load Regulation
    4. 2.4  Load Transient and Loop Response
    5. 2.5  Output Voltage Ripple
    6. 2.6  Input Voltage Ripple
    7. 2.7  Powering Up
    8. 2.8  Powering Down
    9. 2.9  Start-Up Into Pre-Bias
    10. 2.10 Hiccup Mode Current Limit
    11. 2.11 Thermal Performance
  4. 3Board Layout
    1. 3.1 Layout
  5. 4Schematic and Bill of Materials
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
  6. 5Revision History

2.1 Input/Output Connections

The TPS54A24EVM-058 is provided with input/output connectors and test points as shown in Table 2-1. A power supply capable of supplying greater than 7.5 A must be connected to J1 through a pair of 20-AWG wires or better. Banana jacks J5 and J6 provide an alternative connection to input power supply. The load must be connected to J2 through a pair of 20-AWG wires or better. The maximum load current capability is nearly 15 A before the TPS54A24 goes into current limit. Wire lengths must be minimized to reduce losses in the wires. Test point TP1 provides a place to monitor the VIN input voltages with TP7 providing a convenient ground reference. TP4 is used to monitor the output voltage with TP11 as the ground reference.

If modifications are made to the TPS54A24EVM-058 the input current may change. The input power supply and wires connecting the EVM to the power supply must be rated for the input current.

Table 2-1 TPS54A24EVM-058 EVM Connectors and Test Points
REFERENCE DESIGNATORFUNCTION
J1VIN screw terminal to connect input voltage (see Table 1-1 for VIN range)
J2VOUT screw terminal to connect load
J32-pin header for enable. Add shunt to connect EN to ground and disable device.
J42-pin header for power good resistor pull-up connection. Add a shunt to pull up to VOUT. Populate resistor R3 if VOUT is greater than 5 V to keep the PGOOD pin voltage below its 6.5 V abs max rating.
J5Banana jack for positive terminal of input power supply
J6Banana jack for negative terminal of input power supply
TP1VIN test point
TP2EN test point. If applying an external voltage, it must be kept below the EN pin's abs max voltage of 6.5 V.
TP3SW node test point
TP4Output voltage test point
TP5PGOOD test point
TP6PGOOD pull-up test point. Remove the shunt on J4 to provide an external pull-up voltage. The external pull-up voltage must keep the PGOOD pin voltage below its 6.5 V abs max rating.
TP7, TP9, TP11PGND test point
TP8SS/TRK test point
TP10Test point between voltage divider network and output voltage. Used for loop response measurements.
TP12, TP13, TP14AGND test point
TP15SMB connector to measure SW node. When using this test point the scope should be set for 50 Ω termination. The combination of 50 Ω termination and R12||R13 creates a 20:1 attenuation.
TP16SMB connector to measure output voltage. When using this test point the scope should be set for 1 MΩ termination.
TP17Test point for supplying external CLK for synchronization. C2 and R10 should be populated to use this test point.