SLVUBT0A June   2020  – January 2021

 

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Stack-Up Headers

As shown in Figure 3-4, multiple boards can be configured into a master-slave relationship (1 master and up to 5 slaves) and physically stacked upon each other. VCCA and GND are shared between boards on headers J27 and J28. Communication between the boards is shared on header J29. This header, J29, is marked on the bottom silkscreen, as shown in Figure 3-5.

GUID-554867BF-B449-4893-817E-B72AE901E541-low.png Figure 3-4 EVM Masters Slave Configuration
GUID-20201124-CA0I-69WF-JNH9-CM5W10QPMWFC-low.png Figure 3-5 EVM Bottom View Version 2

The J29 signal, nPWRON_S, and the nPWRON/ENABLE or VOUT_LDOVINT signals of the PMIC are connected through J37. When multiple PMICs are stacked, as shown in Figure 3-6, the expectation is that the master is placed in master mode, connecting the stackable signal nPWRON_S, and the VOUT_LDOVINT. By using this stackup configuration, one or more of the slaves power up sequence will always follow the master. When in master mode or when the header J37 is left open the nPWRON/ENABLE pin can be controlled with the EVM push button, S1, or the jumper J45.(1)

GUID-20210111-CA0I-VQBP-8JZB-PLN4H7HGZCJD-low.gif Figure 3-6 Header J37 Master and Slave Select Table Description for 'OPEN' configuration
Table 3-9 Header J37 Master and Slave Select
Configuration Description
Open When used as a single PMIC (no stacking). ENABLE is connected to a pullup and therefore automatically enabled. S1 can be used to generate edges or J45 at any level.(1)
Slave, M/S Select: Closed Slave Mode. The PMIC signal ENABLE is connected to the nPWRON_S signal which is from the master's VOUT_LDOVINT.
M/S Select, Master: Closed Master Mode. The PMIC signal, VOUT_LDOVINT, is connected to the nPWRON_S which will be the ENABLE signal on the PMICs connected as slaves.
The default position for J45 is with pins 1-2 closed so that the pullup is applied to nPWRON/ENABLE.
The default position for J45 is with pins 1-2 closed so that the pullup is applied to nPWRON/ENABLE. J45 is provided so that the signal nPWRON/ENABLE can be pulled low or sourced from an off board signal.