SLVUC07A December   2020  – May 2021 TPS543320

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background
    2. 1.2 Before You Begin
    3. 1.3 Performance Characteristics Summary
  3. 2Configurations and Modifications
    1. 2.1 Output Voltage
    2. 2.2 Switching Frequency (FSEL Pin)
    3. 2.3 Current Limit, Soft-Start Time, and Internal Compensation (MODE Pin)
    4. 2.4 Adjustable UVLO
  4. 3Test Setup and Results
    1. 3.1  Input/Output Connections
    2. 3.2  Efficiency
    3. 3.3  Output Voltage Regulation
    4. 3.4  Load Transient and Loop Response
    5. 3.5  Output Voltage Ripple
    6. 3.6  Input Voltage Ripple
    7. 3.7  Synchronizing to a Clock
    8. 3.8  Start-up and Shutdown with EN
    9. 3.9  Start-up and Shutdown with VIN
    10. 3.10 Hiccup Current Limit
    11. 3.11 Overvoltage Protection
    12. 3.12 Thermal Performance
  5. 4Board Layout
    1. 4.1 Layout
  6. 5Schematic and Bill of Materials
    1. 5.1 Schematic
    2. 5.2 Bill of Materials
  7. 6Revision History

3.11 Overvoltage Protection

Figure 3-32 and Figure 3-33 show the overvoltage protection behavior of U2. This is tested by applying a step to the FB pin with a function generator through the VO_ADJ test point. The VO_ADJ test point is initially equal to the reference voltage of 0.5 V and is stepped up to 3.3 V. The TPS543320 attempts to restart immediately after the OVP fault is cleared. It does not wait for the hiccup time period.

GUID-20201130-CA0I-XMBQ-SL9Z-FRGFXD8J13CP-low.pngFigure 3-32 U2 Overvoltage Protection
GUID-20201130-CA0I-M5L0-CLX5-L9BKNS9NDLG7-low.pngFigure 3-33 U2 OVP and Recover