Because the VOUT is the IC ground in this topology, the EN pin must be referenced to VOUT instead of the ground. In a buck configuration, the specified typical threshold voltage for the enable pin for the TPS6291x is 1.0 V (high) and 0.9 V (low). In the IBB configuration, the VOUT voltage is the reference, so the high threshold is 1.0 V + VOUT and the low threshold is 0.9 V + VOUT. For example, with VOUT = -5 V, then VEN is considered high for voltages above -4 V and low for voltages below -4.1 V. This behavior can cause difficulties for enabling or disabling the part since most applications will not have negative voltages to enable and disable the part. The solution is a logic level shifter, which is implemented on the EVM.

The positive signal that would normally drive the EN signal is not directly connected to the EN/SYNC pin of the TPS6291x. Instead, the signal is tied to the gate of Q1A by using J2. When Q1A is off (J2 jumper installed between EN and GND), Q1B sees 0V across its VGS, and also remains off. In this state, the EN pin sees VOUT, which is below the low level threshold and disables the device.

When the J2 jumper is installed between EN and VIN, this provides enough positive voltage to turn Q1A on (minimum VGS as specified in the MOSFET data sheet), the gate of Q1B is pulled low through Q1A. This drives the VGS of Q1B negative and turns Q1B on. As a consequence, VIN ties to EN through Q2 and the EN/SYNC pin is above the high level threshold, causing the device to turn on. Ensure that the VGD of Q1B remains within the MOSFET ratings during both the enabled and disabled states, or the MOSFETs can be damaged. R2 is an active discharge to accelerate the return to 0V when the J2 jumper is removed.

R3 and R4 can be modified to set a user-selectable input voltage at which the IC turns on.