SLVUCA1
November 2021
TPS7H1210-SEP
Trademarks
1
Introduction
1.1
Features
1.2
Applications
2
Setup
2.1
Input/Output Connectors and Jumper Descriptions
2.1.1
J1, J4 (–)VIN
2.1.2
J6 GND
2.1.3
J2, J5 (–)VOUT
2.1.4
J7 GND
2.1.5
J3 EN
2.1.6
TP1-5 Test Points
2.2
Equipment Setup
3
Operation
4
Adjustable Operation
5
Test Results
5.1
Enable, Disable, and Soft Start Timing
5.2
Output Load Transients
5.3
PSRR
5.4
Noise Spectral Density
6
Board Layout
7
Schematic and Bill of Materials
6
Board Layout
The following images represent the board design layers.
Figure 6-1
Top Overlay Silkscreen
Figure 6-2
Top Solder Mask
Figure 6-3
Top Signal Layer
Figure 6-4
Bottom Signal Layer