SLVUCB3 March   2022

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Related Documentation
  3. 2Schematics, Bill of Materials, and Layout
    1. 2.1 TPS3760EVM Schematic
    2. 2.2 TPS3760EVM Bill of Materials
    3. 2.3 Layout and Component Placement
  4. 3EVM Connectors
    1. 3.1 EVM Test Points
    2. 3.2 EVM Jumpers
  5. 4EVM Setup and Operation
    1. 4.1 Input Power (VDD)
    2. 4.2 SENSE1/SENSE2 Inputs
    3. 4.3 RESET1/RESET2 Outputs
    4. 4.4 Capacitor Time Delay Reset/MR
    5. 4.5 Capacitor Time Delay Sense/MR

4.1 Input Power (VDD)

The VDD supply is connected through the TP6 test point on board. TP6 is connected to the VDD pin of the TPS3760 device and TP5 is connected to the board common GND. The supply voltage range is 2.7V to 65V and a 0.1µF decoupling capacitor is recommended at the input for reducing noise that can propagate through the device (included on the EVM board at C2). Table 4-1 details the nominal supply voltage and typical input decoupling capacitor.

Table 4-1 Nominal Supply Parameters
DeviceNominal Supply Voltage (V)Typical Decoupling Capacitor at Input
TPS3760, TPS3760-Q1 2.7V to 65V0.1 µF