SLVUCD1A May   2022  – September 2024 TPS65219

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Caution
  5. 2Introduction
  6. 3Requirements
    1. 3.1 Hardware
    2. 3.2 Software
  7. 4TPS65219 Resources Overview
  8. 5EVM Configuration
    1. 5.1 Default EVM Configuration
    2. 5.2 Configuration Headers
    3. 5.3 Test Points
  9. 6Graphical User Interface (GUI)
    1. 6.1 Getting Started
      1. 6.1.1 Finding the GUI
      2. 6.1.2 Downloading the Required Software
      3. 6.1.3 Launching the GUI
      4. 6.1.4 Connecting to the EVM
    2. 6.2 Collateral Page
    3. 6.3 Register Map Page
    4. 6.4 NVM Configuration Page
      1. 6.4.1 NVM Fields
      2. 6.4.2 Create and Load a Custom Configuration
    5. 6.5 Sequence Configuration
    6. 6.6 NVM Programming Page
    7. 6.7 Additional Features
  10. 7Schematics, PCB Layouts, and Bill of Materials
    1. 7.1 TPS65219EVM Schematic
    2. 7.2 TPS65219EVM PCB Layers
    3. 7.3 TPS65219EVM Bill of Materials
  11. 8Revision History

2 Introduction

The TPS65219 PMIC is a highly integrated power management design for Arm® Cortex®-A53 Processors and FPGAs. This device combines three step down converters and four low-dropout (LDO) regulators. The Buck1 step down converter can support a load current of up to 3.5A, designed for the core rail of a processor. All three step down converters support non-fixed switching frequency or fixed frequency mode. LDO1 and LDO2 are configurable in both load switch and bypass-mode to support SD-Card configuration. All LDO voltage inputs can be cascaded off the step down converter outputs or use the same system power to enable maximum design and sequencing functionality. Complete with three GPIOs and three Multi-Function-Pins (MFPs), TPS65219 offers the complete package for full control of the power and sequencing of a System on Chip (SoC).