SLVUCD4 November 2022 TPS6594-Q1
As shown in TO_RETENTION, the MCU is powered off and therefore the transition out of the RETENTION to the ACTIVE state must be configured before entering RETENTION. The I2C_6 and I2C_7 triggers must be set depending on the type of retention mode. Below is an example of entering GPIO RETENTION (I2C_6=1) and using TPS65941515 GPIO4 to wake the PMIC into the ACTIVE state.
Write 0x48:0x85:0x40:0x7F //I2C_6 is high
Write 0x48:0x34:0xC0:0x3F //Set GPIO4 to WKUP1 (goes to ACTIVE state)
Write 0x48:0x64:0x08:0xF7 //clear interrupt for GPIO4 falling edge
Write 0x48:0x4F:0x00:0xF7 //unmask interrupt for GPIO4 falling edge
Write 0x48:0x86:0x00:0xFC //trigger the TO_RETENTION power sequence
After the GPIO4 has gone low and the PMIC returns to the ACTIVE state
Write 0x48:0x86:0x03:0xFC //Set NSLEEPx bits for ACTIVE state
Write 0x48:0x64:0x08:0xF7 //clear interrupt of GPIO4
Below is example of entering DDR RETENTION (I2C_7 = 1) and using the TPS65941515 RTC Timer to wake the PMIC into the ACTIVE state.
Write 0x48:0x85:0x80:0x7F // I2C_7 is high
Write 0x48:0xC3:0x01;0xFE // Enable Crystal
Write 0x48:0xC5:0x05:0xF8 // minute timer, enable TIMER interrupts
Write 0x48:0xC2:0x01:0xFE // start timer, if the timer values are non-zero clear before starting
Write 0x48:0x86:0x00:0xFC // trigger the TO_RETENTION power sequence
After the RTC Timer interrupt has occurred and the PMIC returns to the ACTIVE state
Write 0x48:0x86:0x03:0xFC // Set NSLEEPx bits for ACTIVE state
Write 0x48:0xC5:0x00:0xFB // disable timer interrupt, clear bit 2
Write 0x48:0xC4:0x00:0xDF // clear timer interrupt, clear bit 5