SLVUCF6 july   2023

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Requirements
    1. 2.1 Hardware
    2. 2.2 Software
  6. 3TPS65219 Resources Overview
  7. 4EVM Configuration
    1. 4.1 Configuring the USB to I2C Adapter
    2. 4.2 Configuration Headers
    3. 4.3 Test Points
  8. 5NVM Programming
    1. 5.1 TPS65219EVM-SKT default NVM settings
    2. 5.2 NVM programming in Initialize State
    3. 5.3 NVM programming in Initialize State
  9. 6Graphical User Interface (GUI)
    1. 6.1 TPTS65219 EVM Debugging
    2. 6.2 I2C Communication Port and Adapter Debugging
    3. 6.3 Getting Started
      1. 6.3.1 Finding the GUI
      2. 6.3.2 Downloading the Required Software
      3. 6.3.3 Launching the GUI
      4. 6.3.4 Connecting to the EVM
    4. 6.4 Collateral Page
    5. 6.5 Register Map Page
    6. 6.6 NVM Configuration Page
      1. 6.6.1 NVM Fields
      2. 6.6.2 Create / Load a Custom Configuration
    7. 6.7 Sequence Configuration
    8. 6.8 NVM Programming Page
    9. 6.9 Additional Features
  10. 7Schematics, PCB Layouts, and Bill of Materials
    1. 7.1 TPS65219EVM-SKT Schematic
    2. 7.2 TPS65219EVM-SKT PCB Layers
    3. 7.3 TPS65219EVM-RSM Schematic
    4. 7.4 TPS65219EVM-RSM PCB Layers
    5. 7.5 Bill of Materials

1 Introduction

The TPS65219 PMIC is a highly integrated power management solution for ARM® Cortex™ A53 Processors and FPGAs. This device combines 3 step down converters and 4 low-dropout (LDO) regulators. The Buck1 step down converter can support a load current of up to 3.5A, optimal for the core rail of a processor. All 3 step down converters support non-fixed switching frequency or fixed frequency mode. LDO1 and LDO2 are configurable in both load switch and bypass-mode to support SD-Card configuration. All LDO voltage inputs can be cascaded off the step down converter outputs or use the same system power to enable maximum design and sequencing functionality. Complete with 3 GPIOs and 3 Multi-Function-Pins (MFPs), TPS65219 offers the complete package for full control of the power and sequencing of a System on Chip (SoC).