SLVUCF7 March   2022 TLVM13660

 

  1.   Trademarks
  2. 1High-Density EVM Description
    1. 1.1 Typical Applications
    2. 1.2 Features and Electrical Performance
  3. 2EVM Performance Specifications
  4. 3EVM Photo
  5. 4Test Setup and Procedure
    1. 4.1 EVM Connections
    2. 4.2 EVM Setup
    3. 4.3 Test Equipment
    4. 4.4 Recommended Test Setup
      1. 4.4.1 Input Connections
      2. 4.4.2 Output Connections
    5. 4.5 Test Procedure
      1. 4.5.1 Line/Load Regulation and Efficiency
  6. 5Test Data and Performance Curves
    1. 5.1 Efficiency and Load Regulation Performance
    2. 5.2 Waveforms
    3. 5.3 Bode Plot
    4. 5.4 Thermal Performance
    5. 5.5 EMI Performance
  7. 6EVM Documentation
    1. 6.1 Schematic
    2. 6.2 List of Materials
    3. 6.3 PCB Layout
    4. 6.4 Assembly Drawings
    5. 6.5 Multi-Layer Stackup
  8. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
        1. 7.1.1.1 Custom Design With WEBENCH® Tools
    2. 7.2 Documentation Support
      1. 7.2.1 Related Documentation

5.3 Bode Plot

Figure 5-11 provides the bode plot at VIN = 12 V, VOUT = 5 V, and IOUT = 6 A. Figure 5-12 shows a typical capacitance versus voltage curve for a 47-µF, 10-V, X7R output capacitor to highlight the effective capacitance value of a ceramic component. See component details in Section 6.2.

Figure 5-11 Bode Plot with Four 47-µF, 10-V, X7R Output Capacitors (100 µF Effective at 5 VDC, 25°C)
Figure 5-12 Output Capacitance vs. Voltage Derating Curve