In this PDN, the PMIC have the following configured power states:

• PFSM_START
• wait4Enable
• Active (Active SoC)
• S2R (IO + DDR)
• Standby (Partial IO, PMIC OFF)
• TO_SAFE

Figure 6-1 shows the configured PDN power states along with the transition conditions to move between the states. Additionally, the transitions to hardware states, such as SAFE RECOVERY and LP_STANDBY are shown. The hardware states are part of the fixed device power Finite State Machine (FSM) and described in the TPS6593-Q1 data sheet, see TPS65931211-Q1 PMIC User Guide for AM62A TPS65931211-Q1 PMIC User Guide for AM62A User's Guide for Powering AM62A with TPS65931211-Q1 PMIC User's Guide for Powering AM62A with TPS65931211-Q1 PMIC Table of Contents Table of Contents Trademarks Trademarks Introduction Introduction Device Versions Device Versions Processor Connections Processor Connections Power Mapping Power Mapping Supporting 0.85V on VDD_CORE Supporting 0.85V on VDD_CORE Using 5V Input Supply Using 5V Input Supply Control Mapping Control Mapping Supporting Functional Safety ASIL-B Requirements Supporting Functional Safety ASIL-B Requirements Static NVM Settings Static NVM Settings Application-Based Configuration Settings Application-Based Configuration Settings Device Identification Settings Device Identification Settings BUCK Settings BUCK Settings LDO Settings LDO Settings VCCA Settings VCCA Settings GPIO Settings GPIO Settings Finite State Machine (FSM) Settings Finite State Machine (FSM) Settings Interrupt Settings Interrupt Settings POWERGOOD Settings POWERGOOD Settings Miscellaneous Settings Miscellaneous Settings Interface Settings Interface Settings Watchdog Settings Watchdog Settings Pre-Configurable Finite State Machine (PFSM) Settings Pre-Configurable Finite State Machine (PFSM) Settings Configured States Configured States PFSM Triggers PFSM Triggers Power Sequences Power Sequences Sequence: immediateOff2Safe_pd Sequence: immediateOff2Safe_pd Sequence: orderlyOff2safe Sequence: orderlyOff2safe Sequence: warmReset Sequence: warmReset Sequence: any2active Sequence: any2active Sequence: any2_s2r Sequence: any2_s2r Application Examples Application Examples Entering and Exiting S2R (Suspend to RAM) Entering and Exiting S2R (Suspend to RAM) Entering and Exiting Standby Entering and Exiting Standby Entering and Existing LP_STANDBY Entering and Existing LP_STANDBY References References IMPORTANT NOTICE AND DISCLAIMER IMPORTANT NOTICE AND DISCLAIMER TPS65931211-Q1 PMIC User Guide for AM62A A 20220128 Updated title yes TPS65931211-Q1 PMIC User Guide for AM62A A 20220128 Updated title yes A 20220128 Updated title yes A 20220128 Updated title yes A20220128Updated titleyes User's Guide for Powering AM62A with TPS65931211-Q1 PMIC A 20220128 Updated abstract yes This user’s guide can be used as a guide for integrating the TPS65931211-Q1 power management integrated circuit (PMIC) into a system powering the Automotive Sitara AM62A processor. User's Guide for Powering AM62A with TPS65931211-Q1 PMIC A 20220128 Updated abstract yes A 20220128 Updated abstract yes A 20220128 Updated abstract yes A20220128Updated abstractyes This user’s guide can be used as a guide for integrating the TPS65931211-Q1 power management integrated circuit (PMIC) into a system powering the Automotive Sitara AM62A processor. This user’s guide can be used as a guide for integrating the TPS65931211-Q1 power management integrated circuit (PMIC) into a system powering the Automotive Sitara AM62A processor. This user’s guide can be used as a guide for integrating the TPS65931211-Q1 power management integrated circuit (PMIC) into a system powering the Automotive Sitara AM62A processor. This user’s guide can be used as a guide for integrating the TPS65931211-Q1 power management integrated circuit (PMIC) into a system powering the Automotive Sitara AM62A processor. Table of Contents yes Table of Contents yes yes yes Trademarks Trademarks Introduction This user’s guide describes a power distribution network (PDN), using the TPS65931211-Q1 PMIC to supply the Sitara AM62A processor. The following topics are described to clarify platform system operation: PDN power resource connections PDN digital control connections PMIC static NVM configuration PMIC Pre-configurable Mission States PMIC and processor data manuals provide recommended operating conditions, electrical characteristics, recommended external components, package details, register maps, and overall component functionality. In the event of any inconsistency between any user's guide, application report, or other referenced material, the data sheet specification is the definitive source. Introduction This user’s guide describes a power distribution network (PDN), using the TPS65931211-Q1 PMIC to supply the Sitara AM62A processor. The following topics are described to clarify platform system operation: PDN power resource connections PDN digital control connections PMIC static NVM configuration PMIC Pre-configurable Mission States PMIC and processor data manuals provide recommended operating conditions, electrical characteristics, recommended external components, package details, register maps, and overall component functionality. In the event of any inconsistency between any user's guide, application report, or other referenced material, the data sheet specification is the definitive source. This user’s guide describes a power distribution network (PDN), using the TPS65931211-Q1 PMIC to supply the Sitara AM62A processor. The following topics are described to clarify platform system operation: PDN power resource connections PDN digital control connections PMIC static NVM configuration PMIC Pre-configurable Mission States PMIC and processor data manuals provide recommended operating conditions, electrical characteristics, recommended external components, package details, register maps, and overall component functionality. In the event of any inconsistency between any user's guide, application report, or other referenced material, the data sheet specification is the definitive source. This user’s guide describes a power distribution network (PDN), using the TPS65931211-Q1 PMIC to supply the Sitara AM62A processor. The following topics are described to clarify platform system operation: PDN power resource connections PDN digital control connections PMIC static NVM configuration PMIC Pre-configurable Mission States PMIC and processor data manuals provide recommended operating conditions, electrical characteristics, recommended external components, package details, register maps, and overall component functionality. In the event of any inconsistency between any user's guide, application report, or other referenced material, the data sheet specification is the definitive source. PDN power resource connections PDN digital control connections PMIC static NVM configuration PMIC Pre-configurable Mission States PDN power resource connectionsPDN digital control connectionsPMIC static NVM configurationPMIC Pre-configurable Mission States Device Versions There are different orderable part numbers (OPNs) of the TPS6593-Q1 device available with unique NVM settings to support different end product use cases and processor types. The unique NVM settings for each PMIC device are optimized per PDN design to support different processors, processing loads, SDRAM types, system functional safety levels, and end product features (such as low power modes, processor voltages, and memory subsystems). The NVM settings can be identified by both NVM_ID and NVM_REV registers. Each TPS6593 PMIC device is distinguished by the part number, NVM_ID, and NVM_REV. TPS6593-Q1 Orderable Part Number for AM62A PDN USE CASE Orderable Part Number TI_NVM_ID(TI_NVM_REV) Supports Functional Safety up to ASIL-B level. Supports AM62A low power modes (including Partial IO and Suspend to RAM). Up to 10.5 A#GUID-98D37E75-08C1-42C8-9234-C0AFC382A1F0/GUID-EE981061-9DA1-4BB1-8EF9-AE8E05EA3C59 in multiphase (3-phase) configuration to supply the processor CORE rail with selectable 0.75V or 0.85V. Up to 4 A#GUID-98D37E75-08C1-42C8-9234-C0AFC382A1F0/GUID-EE981061-9DA1-4BB1-8EF9-AE8E05EA3C59 to supply the VDDS_DDR with selectable 1.1V for LPDDR4. Supports I/O level of 3.3 V and 1.8 V. Supports optional end product features: Compliant high-speed SD Card memory eMMC eFuse ROM programming supply Compliant USB 2.0 Interface Ethernet PHY HDMI TPS65931211 RWERQ1 0x11 (0x05) TI recommends having 15% margin between the maximum expected load current and the maximum current allowed per each PMIC output rail. Device Versions There are different orderable part numbers (OPNs) of the TPS6593-Q1 device available with unique NVM settings to support different end product use cases and processor types. The unique NVM settings for each PMIC device are optimized per PDN design to support different processors, processing loads, SDRAM types, system functional safety levels, and end product features (such as low power modes, processor voltages, and memory subsystems). The NVM settings can be identified by both NVM_ID and NVM_REV registers. Each TPS6593 PMIC device is distinguished by the part number, NVM_ID, and NVM_REV. TPS6593-Q1 Orderable Part Number for AM62A PDN USE CASE Orderable Part Number TI_NVM_ID(TI_NVM_REV) Supports Functional Safety up to ASIL-B level. Supports AM62A low power modes (including Partial IO and Suspend to RAM). Up to 10.5 A#GUID-98D37E75-08C1-42C8-9234-C0AFC382A1F0/GUID-EE981061-9DA1-4BB1-8EF9-AE8E05EA3C59 in multiphase (3-phase) configuration to supply the processor CORE rail with selectable 0.75V or 0.85V. Up to 4 A#GUID-98D37E75-08C1-42C8-9234-C0AFC382A1F0/GUID-EE981061-9DA1-4BB1-8EF9-AE8E05EA3C59 to supply the VDDS_DDR with selectable 1.1V for LPDDR4. Supports I/O level of 3.3 V and 1.8 V. Supports optional end product features: Compliant high-speed SD Card memory eMMC eFuse ROM programming supply Compliant USB 2.0 Interface Ethernet PHY HDMI TPS65931211 RWERQ1 0x11 (0x05) TI recommends having 15% margin between the maximum expected load current and the maximum current allowed per each PMIC output rail. There are different orderable part numbers (OPNs) of the TPS6593-Q1 device available with unique NVM settings to support different end product use cases and processor types. The unique NVM settings for each PMIC device are optimized per PDN design to support different processors, processing loads, SDRAM types, system functional safety levels, and end product features (such as low power modes, processor voltages, and memory subsystems). The NVM settings can be identified by both NVM_ID and NVM_REV registers. Each TPS6593 PMIC device is distinguished by the part number, NVM_ID, and NVM_REV. TPS6593-Q1 Orderable Part Number for AM62A PDN USE CASE Orderable Part Number TI_NVM_ID(TI_NVM_REV) Supports Functional Safety up to ASIL-B level. Supports AM62A low power modes (including Partial IO and Suspend to RAM). Up to 10.5 A#GUID-98D37E75-08C1-42C8-9234-C0AFC382A1F0/GUID-EE981061-9DA1-4BB1-8EF9-AE8E05EA3C59 in multiphase (3-phase) configuration to supply the processor CORE rail with selectable 0.75V or 0.85V. Up to 4 A#GUID-98D37E75-08C1-42C8-9234-C0AFC382A1F0/GUID-EE981061-9DA1-4BB1-8EF9-AE8E05EA3C59 to supply the VDDS_DDR with selectable 1.1V for LPDDR4. Supports I/O level of 3.3 V and 1.8 V. Supports optional end product features: Compliant high-speed SD Card memory eMMC eFuse ROM programming supply Compliant USB 2.0 Interface Ethernet PHY HDMI TPS65931211 RWERQ1 0x11 (0x05) TI recommends having 15% margin between the maximum expected load current and the maximum current allowed per each PMIC output rail. There are different orderable part numbers (OPNs) of the TPS6593-Q1 device available with unique NVM settings to support different end product use cases and processor types. The unique NVM settings for each PMIC device are optimized per PDN design to support different processors, processing loads, SDRAM types, system functional safety levels, and end product features (such as low power modes, processor voltages, and memory subsystems). The NVM settings can be identified by both NVM_ID and NVM_REV registers. Each TPS6593 PMIC device is distinguished by the part number, NVM_ID, and NVM_REV. TPS6593-Q1 Orderable Part Number for AM62A PDN USE CASE Orderable Part Number TI_NVM_ID(TI_NVM_REV) Supports Functional Safety up to ASIL-B level. Supports AM62A low power modes (including Partial IO and Suspend to RAM). Up to 10.5 A#GUID-98D37E75-08C1-42C8-9234-C0AFC382A1F0/GUID-EE981061-9DA1-4BB1-8EF9-AE8E05EA3C59 in multiphase (3-phase) configuration to supply the processor CORE rail with selectable 0.75V or 0.85V. Up to 4 A#GUID-98D37E75-08C1-42C8-9234-C0AFC382A1F0/GUID-EE981061-9DA1-4BB1-8EF9-AE8E05EA3C59 to supply the VDDS_DDR with selectable 1.1V for LPDDR4. Supports I/O level of 3.3 V and 1.8 V. Supports optional end product features: Compliant high-speed SD Card memory eMMC eFuse ROM programming supply Compliant USB 2.0 Interface Ethernet PHY HDMI TPS65931211 RWERQ1 0x11 (0x05) TPS6593-Q1 Orderable Part Number for AM62A PDN USE CASE Orderable Part Number TI_NVM_ID(TI_NVM_REV) Supports Functional Safety up to ASIL-B level. Supports AM62A low power modes (including Partial IO and Suspend to RAM). Up to 10.5 A#GUID-98D37E75-08C1-42C8-9234-C0AFC382A1F0/GUID-EE981061-9DA1-4BB1-8EF9-AE8E05EA3C59 in multiphase (3-phase) configuration to supply the processor CORE rail with selectable 0.75V or 0.85V. Up to 4 A#GUID-98D37E75-08C1-42C8-9234-C0AFC382A1F0/GUID-EE981061-9DA1-4BB1-8EF9-AE8E05EA3C59 to supply the VDDS_DDR with selectable 1.1V for LPDDR4. Supports I/O level of 3.3 V and 1.8 V. Supports optional end product features: Compliant high-speed SD Card memory eMMC eFuse ROM programming supply Compliant USB 2.0 Interface Ethernet PHY HDMI TPS65931211 RWERQ1 0x11 (0x05) PDN USE CASE Orderable Part Number TI_NVM_ID(TI_NVM_REV) PDN USE CASE Orderable Part Number TI_NVM_ID(TI_NVM_REV) PDN USE CASEOrderable Part NumberTI_NVM_ID(TI_NVM_REV) (TI_NVM_REV) Supports Functional Safety up to ASIL-B level. Supports AM62A low power modes (including Partial IO and Suspend to RAM). Up to 10.5 A#GUID-98D37E75-08C1-42C8-9234-C0AFC382A1F0/GUID-EE981061-9DA1-4BB1-8EF9-AE8E05EA3C59 in multiphase (3-phase) configuration to supply the processor CORE rail with selectable 0.75V or 0.85V. Up to 4 A#GUID-98D37E75-08C1-42C8-9234-C0AFC382A1F0/GUID-EE981061-9DA1-4BB1-8EF9-AE8E05EA3C59 to supply the VDDS_DDR with selectable 1.1V for LPDDR4. Supports I/O level of 3.3 V and 1.8 V. Supports optional end product features: Compliant high-speed SD Card memory eMMC eFuse ROM programming supply Compliant USB 2.0 Interface Ethernet PHY HDMI TPS65931211 RWERQ1 0x11 (0x05) Supports Functional Safety up to ASIL-B level. Supports AM62A low power modes (including Partial IO and Suspend to RAM). Up to 10.5 A#GUID-98D37E75-08C1-42C8-9234-C0AFC382A1F0/GUID-EE981061-9DA1-4BB1-8EF9-AE8E05EA3C59 in multiphase (3-phase) configuration to supply the processor CORE rail with selectable 0.75V or 0.85V. Up to 4 A#GUID-98D37E75-08C1-42C8-9234-C0AFC382A1F0/GUID-EE981061-9DA1-4BB1-8EF9-AE8E05EA3C59 to supply the VDDS_DDR with selectable 1.1V for LPDDR4. Supports I/O level of 3.3 V and 1.8 V. Supports optional end product features: Compliant high-speed SD Card memory eMMC eFuse ROM programming supply Compliant USB 2.0 Interface Ethernet PHY HDMI TPS65931211 RWERQ1 0x11 (0x05) Supports Functional Safety up to ASIL-B level. Supports AM62A low power modes (including Partial IO and Suspend to RAM). Up to 10.5 A#GUID-98D37E75-08C1-42C8-9234-C0AFC382A1F0/GUID-EE981061-9DA1-4BB1-8EF9-AE8E05EA3C59 in multiphase (3-phase) configuration to supply the processor CORE rail with selectable 0.75V or 0.85V. Up to 4 A#GUID-98D37E75-08C1-42C8-9234-C0AFC382A1F0/GUID-EE981061-9DA1-4BB1-8EF9-AE8E05EA3C59 to supply the VDDS_DDR with selectable 1.1V for LPDDR4. Supports I/O level of 3.3 V and 1.8 V. Supports optional end product features: Compliant high-speed SD Card memory eMMC eFuse ROM programming supply Compliant USB 2.0 Interface Ethernet PHY HDMI Supports Functional Safety up to ASIL-B level. Supports AM62A low power modes (including Partial IO and Suspend to RAM). Up to 10.5 A#GUID-98D37E75-08C1-42C8-9234-C0AFC382A1F0/GUID-EE981061-9DA1-4BB1-8EF9-AE8E05EA3C59 in multiphase (3-phase) configuration to supply the processor CORE rail with selectable 0.75V or 0.85V. Up to 4 A#GUID-98D37E75-08C1-42C8-9234-C0AFC382A1F0/GUID-EE981061-9DA1-4BB1-8EF9-AE8E05EA3C59 to supply the VDDS_DDR with selectable 1.1V for LPDDR4. Supports I/O level of 3.3 V and 1.8 V. Supports optional end product features: Compliant high-speed SD Card memory eMMC eFuse ROM programming supply Compliant USB 2.0 Interface Ethernet PHY HDMI Supports Functional Safety up to ASIL-B level.Supports AM62A low power modes (including Partial IO and Suspend to RAM).Up to 10.5 A#GUID-98D37E75-08C1-42C8-9234-C0AFC382A1F0/GUID-EE981061-9DA1-4BB1-8EF9-AE8E05EA3C59 in multiphase (3-phase) configuration to supply the processor CORE rail with selectable 0.75V or 0.85V.#GUID-98D37E75-08C1-42C8-9234-C0AFC382A1F0/GUID-EE981061-9DA1-4BB1-8EF9-AE8E05EA3C59Up to 4 A#GUID-98D37E75-08C1-42C8-9234-C0AFC382A1F0/GUID-EE981061-9DA1-4BB1-8EF9-AE8E05EA3C59 to supply the VDDS_DDR with selectable 1.1V for LPDDR4. #GUID-98D37E75-08C1-42C8-9234-C0AFC382A1F0/GUID-EE981061-9DA1-4BB1-8EF9-AE8E05EA3C59 Supports I/O level of 3.3 V and 1.8 V.Supports optional end product features: Compliant high-speed SD Card memory eMMC eFuse ROM programming supply Compliant USB 2.0 Interface Ethernet PHY HDMI Compliant high-speed SD Card memory eMMC eFuse ROM programming supply Compliant USB 2.0 Interface Ethernet PHY HDMI Compliant high-speed SD Card memoryeMMCeFuse ROM programming supplyCompliant USB 2.0 InterfaceEthernet PHYHDMITPS65931211 RWERQ10x11 (0x05) TI recommends having 15% margin between the maximum expected load current and the maximum current allowed per each PMIC output rail. TI recommends having 15% margin between the maximum expected load current and the maximum current allowed per each PMIC output rail. Processor Connections This section details how the TPS65931211-Q1 power resources and GPIO signals are connected to the processor and other peripheral components. Power Mapping shows the power mapping between the TPS65931211-Q1 PMIC power resources and processor voltage domains. Some of the external peripherals like uSD card, Ethernet PHY and HDMI are optional and might not be needed for the end product. These optional systems peripherals were included in the AM62A SK EVM for development and testing purposes. This PDN uses the TPS6593-Q1 PMIC and discrete power components to meet the power/sequence requirements of the processor and system peripherals. Some of the discrete components are optional depending upon end product features. In this configuration, PMIC uses a 3.3 V input voltage. The TPS22965 Load Switch connects the 3.3V pre-regulator (VSYS_3V3) to the processor 3.3V IO domains. The unused feedback pin, FB_B3, of the TPS65931211-Q1 has been configured per NVM settings, , to provide voltage monitoring for the 3.3V IO domain. This monitoring function enables all of the processor CORE, digital and analog supplies to have voltage monitoring coverage as needed for functional safety ASIL-B systems. LDO1 of the TPS65931211-Q1 PMIC is configured as bypass to supply the SD card dual-voltage I/O (3.3 V and 1.8 V). A processor GPIO control signal with a logic high default value and an external pull-up is used to set SD IO to 3.3 V initially. After the power-up sequence, the processor can set GPIO signal low to select 1.8 V level as needed for high-speed card operation per SD specification. This bypass configuration allows control of the LDO1 voltage from 3.3V to 1.8V without the need to establish I2C communication during boot from SD card operations. The bypass configuration on LDO1 requires connecting its input supply pin (PVIN_LDO12) to 3.3V. The AM62A processor supports multiple low power modes. For the Partial I/O low power mode, the entire SoC is OFF except I/O pins in CANUART I/O bank to maintain wakeup capability. This mode is supported by turning OFF the PMIC and keeping the 3.3V pre-regulator ON to supply VDDSHV_CANUART (3.3V) and an external discrete to supply VDD_CANUART (0.75 V or 0.85 V). The PMIC voltage monitor on FB_B3 must be connected to 3.3 V. If 3.3 V is not connected to FB_B3 when the monitor is enabled then the device goes to the hardware SAFE RECOVERY state, and the processor voltages are disabled. Example Power Connections The external discrete that supplies VDD_CANUART is only needed for Partial IO. When not using Partial IO, VDD_CANUART needs to be connected to the multi-phase Buck1/2/3 and VDDSHV_CANUART can be connected to the same 3.3 V rail that supplies the DVDD3V3(VDDSHVx). identifies which power resources are required to support different system features. PDN Power Mapping and System Features Power Mapping System Features Device Power Resource Voltage Processor Domains Active SoC Partial IO(Low Power Mode) IO + DDR(Low Power Mode) SD Card interface 3.3V pre-regulator(LM5141-Q1) BUCK 3.3V VDDSHV_CANUARTPMIC Supply R R R TLV705075 LDO 0.75V VDD_CANUART R R R TPS65931211-Q1 BUCK123 0.75V or 0.85V VDD_CORE R VDDA_CORE_CSIRX0 R VDDA_CORE_USB R VDDA_DDR_PLL0 R FB_B3 3.3V monitors 3.3V IO domain R R BUCK4 1.1V or 1.2V VDDS_DDR R R BUCK5 1.8V DVDD1V8(VDDSHVy) R R VMON_1P8_SOC O LDO1 3.3V / 1.8V VDDSHV5 O R LDO2 1.8V VPP (eFUSE) O LDO3 0.85V VDDR_CORE R LDO4 1.8V VDDA_1P8_USB R VDDA_TEMP R VDDS_OSC0 R VDDA_MCU R VDDA_PLL R VDDA_1P8_CSIRX0 R TPS22965-Q1 Load Switch 3.3V DVDD3V3(VDDSHVx) R VDDSHV_MCU R VMON_3P3_SOC O VDDA_3P3_USB R TPS62824 BUCK 2.5V VDD_2V5_ETHERNET PHY O TLV75510P LDO 1.0V VDD1P0_ETHERNET PHY O TLV75512P LDO 1.2V CVCC12_HDMI TRANSMITTER O 'R' is required and 'O' is optional. If the multiphase Buck1/2/3 is configured to output 0.85V, both CORE rails on the AM62A (VDD_CORE and VDDR_CORE) are supplied by Buck1/2/3. In this case, LDO3 becomes a free power resource. VMON_3P3_SOC and VMON_1P8_SOC are not supply pins but voltage monitor inputs for the 1.8 V and 3.3 V SoC power supply. If VMON_1P8_SOC and VMON_3P3_SOC are not used to monitor the SOC power rails, they must still be connected to their respective 1.8V and 3.3V power rails. Supporting 0.85V on VDD_CORE In this PDN, VDD_CORE is operating at 0.75V and supplied by the multi-phase Buck1/2/3. VDDR_CORE is supplied by LDO3 (0.85V). However, if BUCK1/2/3 is configured to output 0.85V, then both CORE rails (VDD_CORE and VDDR_CORE) must be supplied by BUCK1/2/3 and LDO3 becomes a free resource. Per AM62A data sheet, VDD_CORE and VDDR_CORE are expected to be powered by the same source so they ramp together when VDD_CORE is operating at 0.85V. LDO3 is configured to be part of the TPS65931211-Q1 power-up sequence and requires an input supply as well as the input/output capacitors to prevent an LDO3 fault condition. The state of GPIO6 sets the output voltage on the multi-phase Buck1/2/3. See for information about polarity of digital pins. Using 5V Input Supply The PDN described in this user's guide was designed for 3.3V input supply. However the TPS65931211-Q1 NVM also supports 5V input supply. The default NVM settings on TPS65931211-Q1 have the UV/OV disabled on VCCA so PMIC can use either voltage (3.3V or 5V). If 5V supply is used, then a 3.3V discrete Buck is required for the 3.3V IO domain instead of a power switch. The external 3.3V Buck can be enabled by GPIO4 and needs to ramp from 0V to 3.3V within the 10ms delay that was assigned to GPIO4 in the any2active sequence. LDO1 is configured as “bypass” and requires a 3.3V supply. This LDO can be supplied by the output of the discrete 3.3V regulator. TI also recommends supplying the remaining LDOs (LDO3 and LDO4) with the discrete 3.3V regulator to reduce power dissipation. VIO_IN must be supplied by 3.3V as well. When using 5V instead of 3.3V, the voltage from the pre-regulator cannot be directly connected to VDDSHV_CANUART. In this case, VDDSHV_CANUART can be supplied by the same discrete 3.3 V Buck that supplies the remaining 3.3 V signals on the processor. Control Mapping shows the digital control signal mapping between processor and PMIC. Specific GPIO pins have been assigned to key signals in order to ensure proper operation. The digital connections allow system features including Partial IO, I/O + DDR, functional safety up to ASIL-B, and compliant dual voltage SD card operation. GPIO4 was configured as push-pull output to enable the external 3.3V power-switch at the beginning of the sequence. GPIO9 and GPIO11 are configured to enable LDO2 (VPP) and LDO1 (SD card interface). The TPS65931211-Q1 enables LDO1 when a rising edge is detected on GPIO11 after nRSTOUT is released and PMIC is in Active state. Similarly, the PMIC enables LDO2 when a rising edge is detected on GPO9 after nRSTOUT is released. GPIO5, GPIO6 and GPIO10 are configured to set the output voltages on some of the PMIC power resources and the state (high or low) for these GPIOs need to be set before the assigned rail turns ON. GPIO5 is configured to set the output voltage on LDO1 to support UHS-I SD cards (3.3V or 1.8V). GPIO6 is configured to set the voltage on the multiphase Buck1/2/3 to support either VDD_CORE voltage (0.75V or 0.85V). GPIO10 is configured to set the voltage on Buck4 to support LPDDR4 (1.1V) or DDR4 (1.2V). The PMIC_LPM_EN0 on the AM62A processor is a dual function control signal used to trigger a Low Power Mode (active low) or PMIC enable (active high). This signal drives the PMIC GPIO3 (nSLEEP2) when triggering IO+DDR mode (suspend to RAM). Alternatively, the PMIC_LPM_EN0 signal can drive the PMIC enable pin when triggering Partial IO low power mode. TPS65931211-Q1 Digital Connections PMIC IO can have distinct power domains for input and output functionality. The SDA function for I2C1 and I2C2 use the VINT voltage domain as an input and the VIO voltage domain as an output. When configured as an input GPIO3 is in the VRTC domain. When configured as an output, GPIO4 is in the VINT domain. Please refer to the device data sheet for a complete description. shows the digital signals on the TPS65931211-Q1 that were configured as open drain and the AM62A domain they must be pulled up to. Open-drain signals and AM62 Power Domain PMIC open drain signal AM62A signal name AM62A Power Domain nINT EXTINTn VDDSHV0 nRSTOUT MCU_PORz VDDS_OSC (1.8V) SCL_I2C1 I2C0_SCL VDDSHV0 SDA_I2C1 I2C0_SDA VDDSHV0 GPIO1 (SCL_I2C2) MCU_I2C0_SCL VDDSHV_MCU GPIO2 (SDA_I2C2) MCU_I2C0_SDA VDDSHV_MCU Please use as a guide to understand GPIO assignments required for each PDN system feature. If the feature listed is not required, the digital connection can be removed; however, the GPIO pin is still configured per NVM defined default function shown. After the processor has booted up, the processor can reconfigure unused GPIOs to support new functions. Reconfiguring a GPIO function is possible as long as that function is only needed after boot and default function does not cause any conflicts with normal operations (for example, two outputs driving same net). Digital Connections by System Feature Device GPIO Mapping System Features PMIC Pin NVM Function Active SoC Functional Safety IO + DDR SD Card TPS65931211-Q1 nPWRON/ ENABLE Enable R R INT INT R R nRSTOUT nRSTOUT R SCL_I2C1 SCL_I2C1 R SDA_I2C1 SDA_I2C1 R GPIO_1 SCL_I2C2 R GPIO_2 SDA_I2C2 R GPIO_3 nSLEEP2 R GPIO_4 GPO(enables 3.3V power-switch) R GPIO_5 GPI(sets output voltage on LDO1) O R GPIO_6 GPI(sets output voltage on BUCK1/2/3) R GPIO_7 nERR_MCU R GPIO_8 DISABLE_WDOG O GPIO_9 GPI(enables/disables LDO2) GPIO_10 GPI(sets output voltage on BUCK4) R GPIO_11 GPI(enables/disables LDO1) R If it is desired to disable the watchdog through hardware, GPIO_8 is required and must be set high by the time nRSTOUT goes high. After nRSTOUT is high, the watchdog state is latched and the pin can be configured for other functions through software. R is Required. O is optional. GPIO5 from the PMIC does not need to be connected to the processor if LDO1 is not used to supply the uSD card interface. Processor Connections This section details how the TPS65931211-Q1 power resources and GPIO signals are connected to the processor and other peripheral components. This section details how the TPS65931211-Q1 power resources and GPIO signals are connected to the processor and other peripheral components. This section details how the TPS65931211-Q1 power resources and GPIO signals are connected to the processor and other peripheral components. Power Mapping shows the power mapping between the TPS65931211-Q1 PMIC power resources and processor voltage domains. Some of the external peripherals like uSD card, Ethernet PHY and HDMI are optional and might not be needed for the end product. These optional systems peripherals were included in the AM62A SK EVM for development and testing purposes. This PDN uses the TPS6593-Q1 PMIC and discrete power components to meet the power/sequence requirements of the processor and system peripherals. Some of the discrete components are optional depending upon end product features. In this configuration, PMIC uses a 3.3 V input voltage. The TPS22965 Load Switch connects the 3.3V pre-regulator (VSYS_3V3) to the processor 3.3V IO domains. The unused feedback pin, FB_B3, of the TPS65931211-Q1 has been configured per NVM settings, , to provide voltage monitoring for the 3.3V IO domain. This monitoring function enables all of the processor CORE, digital and analog supplies to have voltage monitoring coverage as needed for functional safety ASIL-B systems. LDO1 of the TPS65931211-Q1 PMIC is configured as bypass to supply the SD card dual-voltage I/O (3.3 V and 1.8 V). A processor GPIO control signal with a logic high default value and an external pull-up is used to set SD IO to 3.3 V initially. After the power-up sequence, the processor can set GPIO signal low to select 1.8 V level as needed for high-speed card operation per SD specification. This bypass configuration allows control of the LDO1 voltage from 3.3V to 1.8V without the need to establish I2C communication during boot from SD card operations. The bypass configuration on LDO1 requires connecting its input supply pin (PVIN_LDO12) to 3.3V. The AM62A processor supports multiple low power modes. For the Partial I/O low power mode, the entire SoC is OFF except I/O pins in CANUART I/O bank to maintain wakeup capability. This mode is supported by turning OFF the PMIC and keeping the 3.3V pre-regulator ON to supply VDDSHV_CANUART (3.3V) and an external discrete to supply VDD_CANUART (0.75 V or 0.85 V). The PMIC voltage monitor on FB_B3 must be connected to 3.3 V. If 3.3 V is not connected to FB_B3 when the monitor is enabled then the device goes to the hardware SAFE RECOVERY state, and the processor voltages are disabled. Example Power Connections The external discrete that supplies VDD_CANUART is only needed for Partial IO. When not using Partial IO, VDD_CANUART needs to be connected to the multi-phase Buck1/2/3 and VDDSHV_CANUART can be connected to the same 3.3 V rail that supplies the DVDD3V3(VDDSHVx). identifies which power resources are required to support different system features. PDN Power Mapping and System Features Power Mapping System Features Device Power Resource Voltage Processor Domains Active SoC Partial IO(Low Power Mode) IO + DDR(Low Power Mode) SD Card interface 3.3V pre-regulator(LM5141-Q1) BUCK 3.3V VDDSHV_CANUARTPMIC Supply R R R TLV705075 LDO 0.75V VDD_CANUART R R R TPS65931211-Q1 BUCK123 0.75V or 0.85V VDD_CORE R VDDA_CORE_CSIRX0 R VDDA_CORE_USB R VDDA_DDR_PLL0 R FB_B3 3.3V monitors 3.3V IO domain R R BUCK4 1.1V or 1.2V VDDS_DDR R R BUCK5 1.8V DVDD1V8(VDDSHVy) R R VMON_1P8_SOC O LDO1 3.3V / 1.8V VDDSHV5 O R LDO2 1.8V VPP (eFUSE) O LDO3 0.85V VDDR_CORE R LDO4 1.8V VDDA_1P8_USB R VDDA_TEMP R VDDS_OSC0 R VDDA_MCU R VDDA_PLL R VDDA_1P8_CSIRX0 R TPS22965-Q1 Load Switch 3.3V DVDD3V3(VDDSHVx) R VDDSHV_MCU R VMON_3P3_SOC O VDDA_3P3_USB R TPS62824 BUCK 2.5V VDD_2V5_ETHERNET PHY O TLV75510P LDO 1.0V VDD1P0_ETHERNET PHY O TLV75512P LDO 1.2V CVCC12_HDMI TRANSMITTER O 'R' is required and 'O' is optional. If the multiphase Buck1/2/3 is configured to output 0.85V, both CORE rails on the AM62A (VDD_CORE and VDDR_CORE) are supplied by Buck1/2/3. In this case, LDO3 becomes a free power resource. VMON_3P3_SOC and VMON_1P8_SOC are not supply pins but voltage monitor inputs for the 1.8 V and 3.3 V SoC power supply. If VMON_1P8_SOC and VMON_3P3_SOC are not used to monitor the SOC power rails, they must still be connected to their respective 1.8V and 3.3V power rails. Supporting 0.85V on VDD_CORE In this PDN, VDD_CORE is operating at 0.75V and supplied by the multi-phase Buck1/2/3. VDDR_CORE is supplied by LDO3 (0.85V). However, if BUCK1/2/3 is configured to output 0.85V, then both CORE rails (VDD_CORE and VDDR_CORE) must be supplied by BUCK1/2/3 and LDO3 becomes a free resource. Per AM62A data sheet, VDD_CORE and VDDR_CORE are expected to be powered by the same source so they ramp together when VDD_CORE is operating at 0.85V. LDO3 is configured to be part of the TPS65931211-Q1 power-up sequence and requires an input supply as well as the input/output capacitors to prevent an LDO3 fault condition. The state of GPIO6 sets the output voltage on the multi-phase Buck1/2/3. See for information about polarity of digital pins. Using 5V Input Supply The PDN described in this user's guide was designed for 3.3V input supply. However the TPS65931211-Q1 NVM also supports 5V input supply. The default NVM settings on TPS65931211-Q1 have the UV/OV disabled on VCCA so PMIC can use either voltage (3.3V or 5V). If 5V supply is used, then a 3.3V discrete Buck is required for the 3.3V IO domain instead of a power switch. The external 3.3V Buck can be enabled by GPIO4 and needs to ramp from 0V to 3.3V within the 10ms delay that was assigned to GPIO4 in the any2active sequence. LDO1 is configured as “bypass” and requires a 3.3V supply. This LDO can be supplied by the output of the discrete 3.3V regulator. TI also recommends supplying the remaining LDOs (LDO3 and LDO4) with the discrete 3.3V regulator to reduce power dissipation. VIO_IN must be supplied by 3.3V as well. When using 5V instead of 3.3V, the voltage from the pre-regulator cannot be directly connected to VDDSHV_CANUART. In this case, VDDSHV_CANUART can be supplied by the same discrete 3.3 V Buck that supplies the remaining 3.3 V signals on the processor. Power Mapping shows the power mapping between the TPS65931211-Q1 PMIC power resources and processor voltage domains. Some of the external peripherals like uSD card, Ethernet PHY and HDMI are optional and might not be needed for the end product. These optional systems peripherals were included in the AM62A SK EVM for development and testing purposes. This PDN uses the TPS6593-Q1 PMIC and discrete power components to meet the power/sequence requirements of the processor and system peripherals. Some of the discrete components are optional depending upon end product features. In this configuration, PMIC uses a 3.3 V input voltage. The TPS22965 Load Switch connects the 3.3V pre-regulator (VSYS_3V3) to the processor 3.3V IO domains. The unused feedback pin, FB_B3, of the TPS65931211-Q1 has been configured per NVM settings, , to provide voltage monitoring for the 3.3V IO domain. This monitoring function enables all of the processor CORE, digital and analog supplies to have voltage monitoring coverage as needed for functional safety ASIL-B systems. LDO1 of the TPS65931211-Q1 PMIC is configured as bypass to supply the SD card dual-voltage I/O (3.3 V and 1.8 V). A processor GPIO control signal with a logic high default value and an external pull-up is used to set SD IO to 3.3 V initially. After the power-up sequence, the processor can set GPIO signal low to select 1.8 V level as needed for high-speed card operation per SD specification. This bypass configuration allows control of the LDO1 voltage from 3.3V to 1.8V without the need to establish I2C communication during boot from SD card operations. The bypass configuration on LDO1 requires connecting its input supply pin (PVIN_LDO12) to 3.3V. The AM62A processor supports multiple low power modes. For the Partial I/O low power mode, the entire SoC is OFF except I/O pins in CANUART I/O bank to maintain wakeup capability. This mode is supported by turning OFF the PMIC and keeping the 3.3V pre-regulator ON to supply VDDSHV_CANUART (3.3V) and an external discrete to supply VDD_CANUART (0.75 V or 0.85 V). The PMIC voltage monitor on FB_B3 must be connected to 3.3 V. If 3.3 V is not connected to FB_B3 when the monitor is enabled then the device goes to the hardware SAFE RECOVERY state, and the processor voltages are disabled. Example Power Connections The external discrete that supplies VDD_CANUART is only needed for Partial IO. When not using Partial IO, VDD_CANUART needs to be connected to the multi-phase Buck1/2/3 and VDDSHV_CANUART can be connected to the same 3.3 V rail that supplies the DVDD3V3(VDDSHVx). identifies which power resources are required to support different system features. PDN Power Mapping and System Features Power Mapping System Features Device Power Resource Voltage Processor Domains Active SoC Partial IO(Low Power Mode) IO + DDR(Low Power Mode) SD Card interface 3.3V pre-regulator(LM5141-Q1) BUCK 3.3V VDDSHV_CANUARTPMIC Supply R R R TLV705075 LDO 0.75V VDD_CANUART R R R TPS65931211-Q1 BUCK123 0.75V or 0.85V VDD_CORE R VDDA_CORE_CSIRX0 R VDDA_CORE_USB R VDDA_DDR_PLL0 R FB_B3 3.3V monitors 3.3V IO domain R R BUCK4 1.1V or 1.2V VDDS_DDR R R BUCK5 1.8V DVDD1V8(VDDSHVy) R R VMON_1P8_SOC O LDO1 3.3V / 1.8V VDDSHV5 O R LDO2 1.8V VPP (eFUSE) O LDO3 0.85V VDDR_CORE R LDO4 1.8V VDDA_1P8_USB R VDDA_TEMP R VDDS_OSC0 R VDDA_MCU R VDDA_PLL R VDDA_1P8_CSIRX0 R TPS22965-Q1 Load Switch 3.3V DVDD3V3(VDDSHVx) R VDDSHV_MCU R VMON_3P3_SOC O VDDA_3P3_USB R TPS62824 BUCK 2.5V VDD_2V5_ETHERNET PHY O TLV75510P LDO 1.0V VDD1P0_ETHERNET PHY O TLV75512P LDO 1.2V CVCC12_HDMI TRANSMITTER O 'R' is required and 'O' is optional. If the multiphase Buck1/2/3 is configured to output 0.85V, both CORE rails on the AM62A (VDD_CORE and VDDR_CORE) are supplied by Buck1/2/3. In this case, LDO3 becomes a free power resource. VMON_3P3_SOC and VMON_1P8_SOC are not supply pins but voltage monitor inputs for the 1.8 V and 3.3 V SoC power supply. If VMON_1P8_SOC and VMON_3P3_SOC are not used to monitor the SOC power rails, they must still be connected to their respective 1.8V and 3.3V power rails. shows the power mapping between the TPS65931211-Q1 PMIC power resources and processor voltage domains. Some of the external peripherals like uSD card, Ethernet PHY and HDMI are optional and might not be needed for the end product. These optional systems peripherals were included in the AM62A SK EVM for development and testing purposes. This PDN uses the TPS6593-Q1 PMIC and discrete power components to meet the power/sequence requirements of the processor and system peripherals. Some of the discrete components are optional depending upon end product features. In this configuration, PMIC uses a 3.3 V input voltage. The TPS22965 Load Switch connects the 3.3V pre-regulator (VSYS_3V3) to the processor 3.3V IO domains. The unused feedback pin, FB_B3, of the TPS65931211-Q1 has been configured per NVM settings, , to provide voltage monitoring for the 3.3V IO domain. This monitoring function enables all of the processor CORE, digital and analog supplies to have voltage monitoring coverage as needed for functional safety ASIL-B systems. LDO1 of the TPS65931211-Q1 PMIC is configured as bypass to supply the SD card dual-voltage I/O (3.3 V and 1.8 V). A processor GPIO control signal with a logic high default value and an external pull-up is used to set SD IO to 3.3 V initially. After the power-up sequence, the processor can set GPIO signal low to select 1.8 V level as needed for high-speed card operation per SD specification. This bypass configuration allows control of the LDO1 voltage from 3.3V to 1.8V without the need to establish I2C communication during boot from SD card operations. The bypass configuration on LDO1 requires connecting its input supply pin (PVIN_LDO12) to 3.3V. The AM62A processor supports multiple low power modes. For the Partial I/O low power mode, the entire SoC is OFF except I/O pins in CANUART I/O bank to maintain wakeup capability. This mode is supported by turning OFF the PMIC and keeping the 3.3V pre-regulator ON to supply VDDSHV_CANUART (3.3V) and an external discrete to supply VDD_CANUART (0.75 V or 0.85 V). The PMIC voltage monitor on FB_B3 must be connected to 3.3 V. If 3.3 V is not connected to FB_B3 when the monitor is enabled then the device goes to the hardware SAFE RECOVERY state, and the processor voltages are disabled. Example Power Connections The external discrete that supplies VDD_CANUART is only needed for Partial IO. When not using Partial IO, VDD_CANUART needs to be connected to the multi-phase Buck1/2/3 and VDDSHV_CANUART can be connected to the same 3.3 V rail that supplies the DVDD3V3(VDDSHVx). identifies which power resources are required to support different system features. PDN Power Mapping and System Features Power Mapping System Features Device Power Resource Voltage Processor Domains Active SoC Partial IO(Low Power Mode) IO + DDR(Low Power Mode) SD Card interface 3.3V pre-regulator(LM5141-Q1) BUCK 3.3V VDDSHV_CANUARTPMIC Supply R R R TLV705075 LDO 0.75V VDD_CANUART R R R TPS65931211-Q1 BUCK123 0.75V or 0.85V VDD_CORE R VDDA_CORE_CSIRX0 R VDDA_CORE_USB R VDDA_DDR_PLL0 R FB_B3 3.3V monitors 3.3V IO domain R R BUCK4 1.1V or 1.2V VDDS_DDR R R BUCK5 1.8V DVDD1V8(VDDSHVy) R R VMON_1P8_SOC O LDO1 3.3V / 1.8V VDDSHV5 O R LDO2 1.8V VPP (eFUSE) O LDO3 0.85V VDDR_CORE R LDO4 1.8V VDDA_1P8_USB R VDDA_TEMP R VDDS_OSC0 R VDDA_MCU R VDDA_PLL R VDDA_1P8_CSIRX0 R TPS22965-Q1 Load Switch 3.3V DVDD3V3(VDDSHVx) R VDDSHV_MCU R VMON_3P3_SOC O VDDA_3P3_USB R TPS62824 BUCK 2.5V VDD_2V5_ETHERNET PHY O TLV75510P LDO 1.0V VDD1P0_ETHERNET PHY O TLV75512P LDO 1.2V CVCC12_HDMI TRANSMITTER O 'R' is required and 'O' is optional. If the multiphase Buck1/2/3 is configured to output 0.85V, both CORE rails on the AM62A (VDD_CORE and VDDR_CORE) are supplied by Buck1/2/3. In this case, LDO3 becomes a free power resource. VMON_3P3_SOC and VMON_1P8_SOC are not supply pins but voltage monitor inputs for the 1.8 V and 3.3 V SoC power supply. If VMON_1P8_SOC and VMON_3P3_SOC are not used to monitor the SOC power rails, they must still be connected to their respective 1.8V and 3.3V power rails. shows the power mapping between the TPS65931211-Q1 PMIC power resources and processor voltage domains. Some of the external peripherals like uSD card, Ethernet PHY and HDMI are optional and might not be needed for the end product. These optional systems peripherals were included in the AM62A SK EVM for development and testing purposes. This PDN uses the TPS6593-Q1 PMIC and discrete power components to meet the power/sequence requirements of the processor and system peripherals. Some of the discrete components are optional depending upon end product features. In this configuration, PMIC uses a 3.3 V input voltage. The TPS22965 Load Switch connects the 3.3V pre-regulator (VSYS_3V3) to the processor 3.3V IO domains. The unused feedback pin, FB_B3, of the TPS65931211-Q1 has been configured per NVM settings, , to provide voltage monitoring for the 3.3V IO domain. This monitoring function enables all of the processor CORE, digital and analog supplies to have voltage monitoring coverage as needed for functional safety ASIL-B systems. LDO1 of the TPS65931211-Q1 PMIC is configured as bypass to supply the SD card dual-voltage I/O (3.3 V and 1.8 V). A processor GPIO control signal with a logic high default value and an external pull-up is used to set SD IO to 3.3 V initially. After the power-up sequence, the processor can set GPIO signal low to select 1.8 V level as needed for high-speed card operation per SD specification. This bypass configuration allows control of the LDO1 voltage from 3.3V to 1.8V without the need to establish I2C communication during boot from SD card operations. The bypass configuration on LDO1 requires connecting its input supply pin (PVIN_LDO12) to 3.3V.The AM62A processor supports multiple low power modes. For the Partial I/O low power mode, the entire SoC is OFF except I/O pins in CANUART I/O bank to maintain wakeup capability. This mode is supported by turning OFF the PMIC and keeping the 3.3V pre-regulator ON to supply VDDSHV_CANUART (3.3V) and an external discrete to supply VDD_CANUART (0.75 V or 0.85 V). The PMIC voltage monitor on FB_B3 must be connected to 3.3 V. If 3.3 V is not connected to FB_B3 when the monitor is enabled then the device goes to the hardware SAFE RECOVERY state, and the processor voltages are disabled. Example Power Connections The external discrete that supplies VDD_CANUART is only needed for Partial IO. When not using Partial IO, VDD_CANUART needs to be connected to the multi-phase Buck1/2/3 and VDDSHV_CANUART can be connected to the same 3.3 V rail that supplies the DVDD3V3(VDDSHVx). Example Power ConnectionsThe external discrete that supplies VDD_CANUART is only needed for Partial IO. When not using Partial IO, VDD_CANUART needs to be connected to the multi-phase Buck1/2/3 and VDDSHV_CANUART can be connected to the same 3.3 V rail that supplies the DVDD3V3(VDDSHVx). identifies which power resources are required to support different system features. PDN Power Mapping and System Features Power Mapping System Features Device Power Resource Voltage Processor Domains Active SoC Partial IO(Low Power Mode) IO + DDR(Low Power Mode) SD Card interface 3.3V pre-regulator(LM5141-Q1) BUCK 3.3V VDDSHV_CANUARTPMIC Supply R R R TLV705075 LDO 0.75V VDD_CANUART R R R TPS65931211-Q1 BUCK123 0.75V or 0.85V VDD_CORE R VDDA_CORE_CSIRX0 R VDDA_CORE_USB R VDDA_DDR_PLL0 R FB_B3 3.3V monitors 3.3V IO domain R R BUCK4 1.1V or 1.2V VDDS_DDR R R BUCK5 1.8V DVDD1V8(VDDSHVy) R R VMON_1P8_SOC O LDO1 3.3V / 1.8V VDDSHV5 O R LDO2 1.8V VPP (eFUSE) O LDO3 0.85V VDDR_CORE R LDO4 1.8V VDDA_1P8_USB R VDDA_TEMP R VDDS_OSC0 R VDDA_MCU R VDDA_PLL R VDDA_1P8_CSIRX0 R TPS22965-Q1 Load Switch 3.3V DVDD3V3(VDDSHVx) R VDDSHV_MCU R VMON_3P3_SOC O VDDA_3P3_USB R TPS62824 BUCK 2.5V VDD_2V5_ETHERNET PHY O TLV75510P LDO 1.0V VDD1P0_ETHERNET PHY O TLV75512P LDO 1.2V CVCC12_HDMI TRANSMITTER O PDN Power Mapping and System Features Power Mapping System Features Device Power Resource Voltage Processor Domains Active SoC Partial IO(Low Power Mode) IO + DDR(Low Power Mode) SD Card interface 3.3V pre-regulator(LM5141-Q1) BUCK 3.3V VDDSHV_CANUARTPMIC Supply R R R TLV705075 LDO 0.75V VDD_CANUART R R R TPS65931211-Q1 BUCK123 0.75V or 0.85V VDD_CORE R VDDA_CORE_CSIRX0 R VDDA_CORE_USB R VDDA_DDR_PLL0 R FB_B3 3.3V monitors 3.3V IO domain R R BUCK4 1.1V or 1.2V VDDS_DDR R R BUCK5 1.8V DVDD1V8(VDDSHVy) R R VMON_1P8_SOC O LDO1 3.3V / 1.8V VDDSHV5 O R LDO2 1.8V VPP (eFUSE) O LDO3 0.85V VDDR_CORE R LDO4 1.8V VDDA_1P8_USB R VDDA_TEMP R VDDS_OSC0 R VDDA_MCU R VDDA_PLL R VDDA_1P8_CSIRX0 R TPS22965-Q1 Load Switch 3.3V DVDD3V3(VDDSHVx) R VDDSHV_MCU R VMON_3P3_SOC O VDDA_3P3_USB R TPS62824 BUCK 2.5V VDD_2V5_ETHERNET PHY O TLV75510P LDO 1.0V VDD1P0_ETHERNET PHY O TLV75512P LDO 1.2V CVCC12_HDMI TRANSMITTER O Power Mapping System Features Device Power Resource Voltage Processor Domains Active SoC Partial IO(Low Power Mode) IO + DDR(Low Power Mode) SD Card interface Power Mapping System Features Power MappingSystem Features Device Power Resource Voltage Processor Domains Active SoC Partial IO(Low Power Mode) IO + DDR(Low Power Mode) SD Card interface DevicePower ResourceVoltageProcessor DomainsActive SoCPartial IO(Low Power Mode) (Low Power Mode)IO + DDR(Low Power Mode) (Low Power Mode)SD Card interface 3.3V pre-regulator(LM5141-Q1) BUCK 3.3V VDDSHV_CANUARTPMIC Supply R R R TLV705075 LDO 0.75V VDD_CANUART R R R TPS65931211-Q1 BUCK123 0.75V or 0.85V VDD_CORE R VDDA_CORE_CSIRX0 R VDDA_CORE_USB R VDDA_DDR_PLL0 R FB_B3 3.3V monitors 3.3V IO domain R R BUCK4 1.1V or 1.2V VDDS_DDR R R BUCK5 1.8V DVDD1V8(VDDSHVy) R R VMON_1P8_SOC O LDO1 3.3V / 1.8V VDDSHV5 O R LDO2 1.8V VPP (eFUSE) O LDO3 0.85V VDDR_CORE R LDO4 1.8V VDDA_1P8_USB R VDDA_TEMP R VDDS_OSC0 R VDDA_MCU R VDDA_PLL R VDDA_1P8_CSIRX0 R TPS22965-Q1 Load Switch 3.3V DVDD3V3(VDDSHVx) R VDDSHV_MCU R VMON_3P3_SOC O VDDA_3P3_USB R TPS62824 BUCK 2.5V VDD_2V5_ETHERNET PHY O TLV75510P LDO 1.0V VDD1P0_ETHERNET PHY O TLV75512P LDO 1.2V CVCC12_HDMI TRANSMITTER O 3.3V pre-regulator(LM5141-Q1) BUCK 3.3V VDDSHV_CANUARTPMIC Supply R R R 3.3V pre-regulator(LM5141-Q1) (LM5141-Q1)BUCK3.3VVDDSHV_CANUARTPMIC Supply PMIC SupplyRRR TLV705075 LDO 0.75V VDD_CANUART R R R TLV705075LDO0.75VVDD_CANUARTRRR TPS65931211-Q1 BUCK123 0.75V or 0.85V VDD_CORE R TPS65931211-Q1BUCK1230.75V or 0.85V VDD_CORER VDDA_CORE_CSIRX0 R VDDA_CORE_CSIRX0R VDDA_CORE_USB R VDDA_CORE_USBR VDDA_DDR_PLL0 R VDDA_DDR_PLL0R FB_B3 3.3V monitors 3.3V IO domain R R FB_B33.3Vmonitors 3.3V IO domainRR BUCK4 1.1V or 1.2V VDDS_DDR R R BUCK41.1V or 1.2VVDDS_DDRRR BUCK5 1.8V DVDD1V8(VDDSHVy) R R BUCK51.8VDVDD1V8(VDDSHVy)RR VMON_1P8_SOC O VMON_1P8_SOC O LDO1 3.3V / 1.8V VDDSHV5 O R LDO13.3V / 1.8VVDDSHV5OR LDO2 1.8V VPP (eFUSE) O LDO21.8VVPP (eFUSE)O LDO3 0.85V VDDR_CORE R LDO30.85V VDDR_CORER LDO4 1.8V VDDA_1P8_USB R LDO41.8VVDDA_1P8_USBR VDDA_TEMP R VDDA_TEMPR VDDS_OSC0 R VDDS_OSC0R VDDA_MCU R VDDA_MCUR VDDA_PLL R VDDA_PLLR VDDA_1P8_CSIRX0 R VDDA_1P8_CSIRX0R TPS22965-Q1 Load Switch 3.3V DVDD3V3(VDDSHVx) R TPS22965-Q1Load Switch3.3VDVDD3V3(VDDSHVx)R VDDSHV_MCU R VDDSHV_MCUR VMON_3P3_SOC O VMON_3P3_SOC O VDDA_3P3_USB R VDDA_3P3_USBR TPS62824 BUCK 2.5V VDD_2V5_ETHERNET PHY O TPS62824BUCK2.5VVDD_2V5_ETHERNET PHYO TLV75510P LDO 1.0V VDD1P0_ETHERNET PHY O TLV75510PLDO1.0VVDD1P0_ETHERNET PHYO TLV75512P LDO 1.2V CVCC12_HDMI TRANSMITTER O TLV75512PLDO1.2VCVCC12_HDMI TRANSMITTERO 'R' is required and 'O' is optional. If the multiphase Buck1/2/3 is configured to output 0.85V, both CORE rails on the AM62A (VDD_CORE and VDDR_CORE) are supplied by Buck1/2/3. In this case, LDO3 becomes a free power resource. VMON_3P3_SOC and VMON_1P8_SOC are not supply pins but voltage monitor inputs for the 1.8 V and 3.3 V SoC power supply. If VMON_1P8_SOC and VMON_3P3_SOC are not used to monitor the SOC power rails, they must still be connected to their respective 1.8V and 3.3V power rails. 'R' is required and 'O' is optional.If the multiphase Buck1/2/3 is configured to output 0.85V, both CORE rails on the AM62A (VDD_CORE and VDDR_CORE) are supplied by Buck1/2/3. In this case, LDO3 becomes a free power resource. VMON_3P3_SOC and VMON_1P8_SOC are not supply pins but voltage monitor inputs for the 1.8 V and 3.3 V SoC power supply. If VMON_1P8_SOC and VMON_3P3_SOC are not used to monitor the SOC power rails, they must still be connected to their respective 1.8V and 3.3V power rails. Supporting 0.85V on VDD_CORE In this PDN, VDD_CORE is operating at 0.75V and supplied by the multi-phase Buck1/2/3. VDDR_CORE is supplied by LDO3 (0.85V). However, if BUCK1/2/3 is configured to output 0.85V, then both CORE rails (VDD_CORE and VDDR_CORE) must be supplied by BUCK1/2/3 and LDO3 becomes a free resource. Per AM62A data sheet, VDD_CORE and VDDR_CORE are expected to be powered by the same source so they ramp together when VDD_CORE is operating at 0.85V. LDO3 is configured to be part of the TPS65931211-Q1 power-up sequence and requires an input supply as well as the input/output capacitors to prevent an LDO3 fault condition. The state of GPIO6 sets the output voltage on the multi-phase Buck1/2/3. See for information about polarity of digital pins. Supporting 0.85V on VDD_CORE In this PDN, VDD_CORE is operating at 0.75V and supplied by the multi-phase Buck1/2/3. VDDR_CORE is supplied by LDO3 (0.85V). However, if BUCK1/2/3 is configured to output 0.85V, then both CORE rails (VDD_CORE and VDDR_CORE) must be supplied by BUCK1/2/3 and LDO3 becomes a free resource. Per AM62A data sheet, VDD_CORE and VDDR_CORE are expected to be powered by the same source so they ramp together when VDD_CORE is operating at 0.85V. LDO3 is configured to be part of the TPS65931211-Q1 power-up sequence and requires an input supply as well as the input/output capacitors to prevent an LDO3 fault condition. The state of GPIO6 sets the output voltage on the multi-phase Buck1/2/3. See for information about polarity of digital pins. In this PDN, VDD_CORE is operating at 0.75V and supplied by the multi-phase Buck1/2/3. VDDR_CORE is supplied by LDO3 (0.85V). However, if BUCK1/2/3 is configured to output 0.85V, then both CORE rails (VDD_CORE and VDDR_CORE) must be supplied by BUCK1/2/3 and LDO3 becomes a free resource. Per AM62A data sheet, VDD_CORE and VDDR_CORE are expected to be powered by the same source so they ramp together when VDD_CORE is operating at 0.85V. LDO3 is configured to be part of the TPS65931211-Q1 power-up sequence and requires an input supply as well as the input/output capacitors to prevent an LDO3 fault condition. The state of GPIO6 sets the output voltage on the multi-phase Buck1/2/3. See for information about polarity of digital pins. Using 5V Input Supply The PDN described in this user's guide was designed for 3.3V input supply. However the TPS65931211-Q1 NVM also supports 5V input supply. The default NVM settings on TPS65931211-Q1 have the UV/OV disabled on VCCA so PMIC can use either voltage (3.3V or 5V). If 5V supply is used, then a 3.3V discrete Buck is required for the 3.3V IO domain instead of a power switch. The external 3.3V Buck can be enabled by GPIO4 and needs to ramp from 0V to 3.3V within the 10ms delay that was assigned to GPIO4 in the any2active sequence. LDO1 is configured as “bypass” and requires a 3.3V supply. This LDO can be supplied by the output of the discrete 3.3V regulator. TI also recommends supplying the remaining LDOs (LDO3 and LDO4) with the discrete 3.3V regulator to reduce power dissipation. VIO_IN must be supplied by 3.3V as well. When using 5V instead of 3.3V, the voltage from the pre-regulator cannot be directly connected to VDDSHV_CANUART. In this case, VDDSHV_CANUART can be supplied by the same discrete 3.3 V Buck that supplies the remaining 3.3 V signals on the processor. Using 5V Input Supply The PDN described in this user's guide was designed for 3.3V input supply. However the TPS65931211-Q1 NVM also supports 5V input supply. The default NVM settings on TPS65931211-Q1 have the UV/OV disabled on VCCA so PMIC can use either voltage (3.3V or 5V). If 5V supply is used, then a 3.3V discrete Buck is required for the 3.3V IO domain instead of a power switch. The external 3.3V Buck can be enabled by GPIO4 and needs to ramp from 0V to 3.3V within the 10ms delay that was assigned to GPIO4 in the any2active sequence. LDO1 is configured as “bypass” and requires a 3.3V supply. This LDO can be supplied by the output of the discrete 3.3V regulator. TI also recommends supplying the remaining LDOs (LDO3 and LDO4) with the discrete 3.3V regulator to reduce power dissipation. VIO_IN must be supplied by 3.3V as well. When using 5V instead of 3.3V, the voltage from the pre-regulator cannot be directly connected to VDDSHV_CANUART. In this case, VDDSHV_CANUART can be supplied by the same discrete 3.3 V Buck that supplies the remaining 3.3 V signals on the processor. The PDN described in this user's guide was designed for 3.3V input supply. However the TPS65931211-Q1 NVM also supports 5V input supply. The default NVM settings on TPS65931211-Q1 have the UV/OV disabled on VCCA so PMIC can use either voltage (3.3V or 5V). If 5V supply is used, then a 3.3V discrete Buck is required for the 3.3V IO domain instead of a power switch. The external 3.3V Buck can be enabled by GPIO4 and needs to ramp from 0V to 3.3V within the 10ms delay that was assigned to GPIO4 in the any2active sequence. LDO1 is configured as “bypass” and requires a 3.3V supply. This LDO can be supplied by the output of the discrete 3.3V regulator. TI also recommends supplying the remaining LDOs (LDO3 and LDO4) with the discrete 3.3V regulator to reduce power dissipation. VIO_IN must be supplied by 3.3V as well. When using 5V instead of 3.3V, the voltage from the pre-regulator cannot be directly connected to VDDSHV_CANUART. In this case, VDDSHV_CANUART can be supplied by the same discrete 3.3 V Buck that supplies the remaining 3.3 V signals on the processor. The PDN described in this user's guide was designed for 3.3V input supply. However the TPS65931211-Q1 NVM also supports 5V input supply. The default NVM settings on TPS65931211-Q1 have the UV/OV disabled on VCCA so PMIC can use either voltage (3.3V or 5V). If 5V supply is used, then a 3.3V discrete Buck is required for the 3.3V IO domain instead of a power switch. The external 3.3V Buck can be enabled by GPIO4 and needs to ramp from 0V to 3.3V within the 10ms delay that was assigned to GPIO4 in the any2active sequence. LDO1 is configured as “bypass” and requires a 3.3V supply. This LDO can be supplied by the output of the discrete 3.3V regulator. TI also recommends supplying the remaining LDOs (LDO3 and LDO4) with the discrete 3.3V regulator to reduce power dissipation. VIO_IN must be supplied by 3.3V as well.When using 5V instead of 3.3V, the voltage from the pre-regulator cannot be directly connected to VDDSHV_CANUART. In this case, VDDSHV_CANUART can be supplied by the same discrete 3.3 V Buck that supplies the remaining 3.3 V signals on the processor. Control Mapping shows the digital control signal mapping between processor and PMIC. Specific GPIO pins have been assigned to key signals in order to ensure proper operation. The digital connections allow system features including Partial IO, I/O + DDR, functional safety up to ASIL-B, and compliant dual voltage SD card operation. GPIO4 was configured as push-pull output to enable the external 3.3V power-switch at the beginning of the sequence. GPIO9 and GPIO11 are configured to enable LDO2 (VPP) and LDO1 (SD card interface). The TPS65931211-Q1 enables LDO1 when a rising edge is detected on GPIO11 after nRSTOUT is released and PMIC is in Active state. Similarly, the PMIC enables LDO2 when a rising edge is detected on GPO9 after nRSTOUT is released. GPIO5, GPIO6 and GPIO10 are configured to set the output voltages on some of the PMIC power resources and the state (high or low) for these GPIOs need to be set before the assigned rail turns ON. GPIO5 is configured to set the output voltage on LDO1 to support UHS-I SD cards (3.3V or 1.8V). GPIO6 is configured to set the voltage on the multiphase Buck1/2/3 to support either VDD_CORE voltage (0.75V or 0.85V). GPIO10 is configured to set the voltage on Buck4 to support LPDDR4 (1.1V) or DDR4 (1.2V). The PMIC_LPM_EN0 on the AM62A processor is a dual function control signal used to trigger a Low Power Mode (active low) or PMIC enable (active high). This signal drives the PMIC GPIO3 (nSLEEP2) when triggering IO+DDR mode (suspend to RAM). Alternatively, the PMIC_LPM_EN0 signal can drive the PMIC enable pin when triggering Partial IO low power mode. TPS65931211-Q1 Digital Connections PMIC IO can have distinct power domains for input and output functionality. The SDA function for I2C1 and I2C2 use the VINT voltage domain as an input and the VIO voltage domain as an output. When configured as an input GPIO3 is in the VRTC domain. When configured as an output, GPIO4 is in the VINT domain. Please refer to the device data sheet for a complete description. shows the digital signals on the TPS65931211-Q1 that were configured as open drain and the AM62A domain they must be pulled up to. Open-drain signals and AM62 Power Domain PMIC open drain signal AM62A signal name AM62A Power Domain nINT EXTINTn VDDSHV0 nRSTOUT MCU_PORz VDDS_OSC (1.8V) SCL_I2C1 I2C0_SCL VDDSHV0 SDA_I2C1 I2C0_SDA VDDSHV0 GPIO1 (SCL_I2C2) MCU_I2C0_SCL VDDSHV_MCU GPIO2 (SDA_I2C2) MCU_I2C0_SDA VDDSHV_MCU Please use as a guide to understand GPIO assignments required for each PDN system feature. If the feature listed is not required, the digital connection can be removed; however, the GPIO pin is still configured per NVM defined default function shown. After the processor has booted up, the processor can reconfigure unused GPIOs to support new functions. Reconfiguring a GPIO function is possible as long as that function is only needed after boot and default function does not cause any conflicts with normal operations (for example, two outputs driving same net). Digital Connections by System Feature Device GPIO Mapping System Features PMIC Pin NVM Function Active SoC Functional Safety IO + DDR SD Card TPS65931211-Q1 nPWRON/ ENABLE Enable R R INT INT R R nRSTOUT nRSTOUT R SCL_I2C1 SCL_I2C1 R SDA_I2C1 SDA_I2C1 R GPIO_1 SCL_I2C2 R GPIO_2 SDA_I2C2 R GPIO_3 nSLEEP2 R GPIO_4 GPO(enables 3.3V power-switch) R GPIO_5 GPI(sets output voltage on LDO1) O R GPIO_6 GPI(sets output voltage on BUCK1/2/3) R GPIO_7 nERR_MCU R GPIO_8 DISABLE_WDOG O GPIO_9 GPI(enables/disables LDO2) GPIO_10 GPI(sets output voltage on BUCK4) R GPIO_11 GPI(enables/disables LDO1) R If it is desired to disable the watchdog through hardware, GPIO_8 is required and must be set high by the time nRSTOUT goes high. After nRSTOUT is high, the watchdog state is latched and the pin can be configured for other functions through software. R is Required. O is optional. GPIO5 from the PMIC does not need to be connected to the processor if LDO1 is not used to supply the uSD card interface. Control Mapping shows the digital control signal mapping between processor and PMIC. Specific GPIO pins have been assigned to key signals in order to ensure proper operation. The digital connections allow system features including Partial IO, I/O + DDR, functional safety up to ASIL-B, and compliant dual voltage SD card operation. GPIO4 was configured as push-pull output to enable the external 3.3V power-switch at the beginning of the sequence. GPIO9 and GPIO11 are configured to enable LDO2 (VPP) and LDO1 (SD card interface). The TPS65931211-Q1 enables LDO1 when a rising edge is detected on GPIO11 after nRSTOUT is released and PMIC is in Active state. Similarly, the PMIC enables LDO2 when a rising edge is detected on GPO9 after nRSTOUT is released. GPIO5, GPIO6 and GPIO10 are configured to set the output voltages on some of the PMIC power resources and the state (high or low) for these GPIOs need to be set before the assigned rail turns ON. GPIO5 is configured to set the output voltage on LDO1 to support UHS-I SD cards (3.3V or 1.8V). GPIO6 is configured to set the voltage on the multiphase Buck1/2/3 to support either VDD_CORE voltage (0.75V or 0.85V). GPIO10 is configured to set the voltage on Buck4 to support LPDDR4 (1.1V) or DDR4 (1.2V). The PMIC_LPM_EN0 on the AM62A processor is a dual function control signal used to trigger a Low Power Mode (active low) or PMIC enable (active high). This signal drives the PMIC GPIO3 (nSLEEP2) when triggering IO+DDR mode (suspend to RAM). Alternatively, the PMIC_LPM_EN0 signal can drive the PMIC enable pin when triggering Partial IO low power mode. TPS65931211-Q1 Digital Connections PMIC IO can have distinct power domains for input and output functionality. The SDA function for I2C1 and I2C2 use the VINT voltage domain as an input and the VIO voltage domain as an output. When configured as an input GPIO3 is in the VRTC domain. When configured as an output, GPIO4 is in the VINT domain. Please refer to the device data sheet for a complete description. shows the digital signals on the TPS65931211-Q1 that were configured as open drain and the AM62A domain they must be pulled up to. Open-drain signals and AM62 Power Domain PMIC open drain signal AM62A signal name AM62A Power Domain nINT EXTINTn VDDSHV0 nRSTOUT MCU_PORz VDDS_OSC (1.8V) SCL_I2C1 I2C0_SCL VDDSHV0 SDA_I2C1 I2C0_SDA VDDSHV0 GPIO1 (SCL_I2C2) MCU_I2C0_SCL VDDSHV_MCU GPIO2 (SDA_I2C2) MCU_I2C0_SDA VDDSHV_MCU Please use as a guide to understand GPIO assignments required for each PDN system feature. If the feature listed is not required, the digital connection can be removed; however, the GPIO pin is still configured per NVM defined default function shown. After the processor has booted up, the processor can reconfigure unused GPIOs to support new functions. Reconfiguring a GPIO function is possible as long as that function is only needed after boot and default function does not cause any conflicts with normal operations (for example, two outputs driving same net). Digital Connections by System Feature Device GPIO Mapping System Features PMIC Pin NVM Function Active SoC Functional Safety IO + DDR SD Card TPS65931211-Q1 nPWRON/ ENABLE Enable R R INT INT R R nRSTOUT nRSTOUT R SCL_I2C1 SCL_I2C1 R SDA_I2C1 SDA_I2C1 R GPIO_1 SCL_I2C2 R GPIO_2 SDA_I2C2 R GPIO_3 nSLEEP2 R GPIO_4 GPO(enables 3.3V power-switch) R GPIO_5 GPI(sets output voltage on LDO1) O R GPIO_6 GPI(sets output voltage on BUCK1/2/3) R GPIO_7 nERR_MCU R GPIO_8 DISABLE_WDOG O GPIO_9 GPI(enables/disables LDO2) GPIO_10 GPI(sets output voltage on BUCK4) R GPIO_11 GPI(enables/disables LDO1) R If it is desired to disable the watchdog through hardware, GPIO_8 is required and must be set high by the time nRSTOUT goes high. After nRSTOUT is high, the watchdog state is latched and the pin can be configured for other functions through software. R is Required. O is optional. GPIO5 from the PMIC does not need to be connected to the processor if LDO1 is not used to supply the uSD card interface. shows the digital control signal mapping between processor and PMIC. Specific GPIO pins have been assigned to key signals in order to ensure proper operation. The digital connections allow system features including Partial IO, I/O + DDR, functional safety up to ASIL-B, and compliant dual voltage SD card operation. GPIO4 was configured as push-pull output to enable the external 3.3V power-switch at the beginning of the sequence. GPIO9 and GPIO11 are configured to enable LDO2 (VPP) and LDO1 (SD card interface). The TPS65931211-Q1 enables LDO1 when a rising edge is detected on GPIO11 after nRSTOUT is released and PMIC is in Active state. Similarly, the PMIC enables LDO2 when a rising edge is detected on GPO9 after nRSTOUT is released. GPIO5, GPIO6 and GPIO10 are configured to set the output voltages on some of the PMIC power resources and the state (high or low) for these GPIOs need to be set before the assigned rail turns ON. GPIO5 is configured to set the output voltage on LDO1 to support UHS-I SD cards (3.3V or 1.8V). GPIO6 is configured to set the voltage on the multiphase Buck1/2/3 to support either VDD_CORE voltage (0.75V or 0.85V). GPIO10 is configured to set the voltage on Buck4 to support LPDDR4 (1.1V) or DDR4 (1.2V). The PMIC_LPM_EN0 on the AM62A processor is a dual function control signal used to trigger a Low Power Mode (active low) or PMIC enable (active high). This signal drives the PMIC GPIO3 (nSLEEP2) when triggering IO+DDR mode (suspend to RAM). Alternatively, the PMIC_LPM_EN0 signal can drive the PMIC enable pin when triggering Partial IO low power mode. TPS65931211-Q1 Digital Connections PMIC IO can have distinct power domains for input and output functionality. The SDA function for I2C1 and I2C2 use the VINT voltage domain as an input and the VIO voltage domain as an output. When configured as an input GPIO3 is in the VRTC domain. When configured as an output, GPIO4 is in the VINT domain. Please refer to the device data sheet for a complete description. shows the digital signals on the TPS65931211-Q1 that were configured as open drain and the AM62A domain they must be pulled up to. Open-drain signals and AM62 Power Domain PMIC open drain signal AM62A signal name AM62A Power Domain nINT EXTINTn VDDSHV0 nRSTOUT MCU_PORz VDDS_OSC (1.8V) SCL_I2C1 I2C0_SCL VDDSHV0 SDA_I2C1 I2C0_SDA VDDSHV0 GPIO1 (SCL_I2C2) MCU_I2C0_SCL VDDSHV_MCU GPIO2 (SDA_I2C2) MCU_I2C0_SDA VDDSHV_MCU Please use as a guide to understand GPIO assignments required for each PDN system feature. If the feature listed is not required, the digital connection can be removed; however, the GPIO pin is still configured per NVM defined default function shown. After the processor has booted up, the processor can reconfigure unused GPIOs to support new functions. Reconfiguring a GPIO function is possible as long as that function is only needed after boot and default function does not cause any conflicts with normal operations (for example, two outputs driving same net). Digital Connections by System Feature Device GPIO Mapping System Features PMIC Pin NVM Function Active SoC Functional Safety IO + DDR SD Card TPS65931211-Q1 nPWRON/ ENABLE Enable R R INT INT R R nRSTOUT nRSTOUT R SCL_I2C1 SCL_I2C1 R SDA_I2C1 SDA_I2C1 R GPIO_1 SCL_I2C2 R GPIO_2 SDA_I2C2 R GPIO_3 nSLEEP2 R GPIO_4 GPO(enables 3.3V power-switch) R GPIO_5 GPI(sets output voltage on LDO1) O R GPIO_6 GPI(sets output voltage on BUCK1/2/3) R GPIO_7 nERR_MCU R GPIO_8 DISABLE_WDOG O GPIO_9 GPI(enables/disables LDO2) GPIO_10 GPI(sets output voltage on BUCK4) R GPIO_11 GPI(enables/disables LDO1) R If it is desired to disable the watchdog through hardware, GPIO_8 is required and must be set high by the time nRSTOUT goes high. After nRSTOUT is high, the watchdog state is latched and the pin can be configured for other functions through software. R is Required. O is optional. GPIO5 from the PMIC does not need to be connected to the processor if LDO1 is not used to supply the uSD card interface. shows the digital control signal mapping between processor and PMIC. Specific GPIO pins have been assigned to key signals in order to ensure proper operation. The digital connections allow system features including Partial IO, I/O + DDR, functional safety up to ASIL-B, and compliant dual voltage SD card operation. GPIO4 was configured as push-pull output to enable the external 3.3V power-switch at the beginning of the sequence. GPIO9 and GPIO11 are configured to enable LDO2 (VPP) and LDO1 (SD card interface). The TPS65931211-Q1 enables LDO1 when a rising edge is detected on GPIO11 after nRSTOUT is released and PMIC is in Active state. Similarly, the PMIC enables LDO2 when a rising edge is detected on GPO9 after nRSTOUT is released. GPIO5, GPIO6 and GPIO10 are configured to set the output voltages on some of the PMIC power resources and the state (high or low) for these GPIOs need to be set before the assigned rail turns ON. GPIO5 is configured to set the output voltage on LDO1 to support UHS-I SD cards (3.3V or 1.8V). GPIO6 is configured to set the voltage on the multiphase Buck1/2/3 to support either VDD_CORE voltage (0.75V or 0.85V). GPIO10 is configured to set the voltage on Buck4 to support LPDDR4 (1.1V) or DDR4 (1.2V). The PMIC_LPM_EN0 on the AM62A processor is a dual function control signal used to trigger a Low Power Mode (active low) or PMIC enable (active high). This signal drives the PMIC GPIO3 (nSLEEP2) when triggering IO+DDR mode (suspend to RAM). Alternatively, the PMIC_LPM_EN0 signal can drive the PMIC enable pin when triggering Partial IO low power mode. TPS65931211-Q1 Digital Connections TPS65931211-Q1 Digital ConnectionsPMIC IO can have distinct power domains for input and output functionality. The SDA function for I2C1 and I2C2 use the VINT voltage domain as an input and the VIO voltage domain as an output. When configured as an input GPIO3 is in the VRTC domain. When configured as an output, GPIO4 is in the VINT domain. Please refer to the device data sheet for a complete description. data sheet shows the digital signals on the TPS65931211-Q1 that were configured as open drain and the AM62A domain they must be pulled up to. Open-drain signals and AM62 Power Domain PMIC open drain signal AM62A signal name AM62A Power Domain nINT EXTINTn VDDSHV0 nRSTOUT MCU_PORz VDDS_OSC (1.8V) SCL_I2C1 I2C0_SCL VDDSHV0 SDA_I2C1 I2C0_SDA VDDSHV0 GPIO1 (SCL_I2C2) MCU_I2C0_SCL VDDSHV_MCU GPIO2 (SDA_I2C2) MCU_I2C0_SDA VDDSHV_MCU Open-drain signals and AM62 Power Domain PMIC open drain signal AM62A signal name AM62A Power Domain nINT EXTINTn VDDSHV0 nRSTOUT MCU_PORz VDDS_OSC (1.8V) SCL_I2C1 I2C0_SCL VDDSHV0 SDA_I2C1 I2C0_SDA VDDSHV0 GPIO1 (SCL_I2C2) MCU_I2C0_SCL VDDSHV_MCU GPIO2 (SDA_I2C2) MCU_I2C0_SDA VDDSHV_MCU PMIC open drain signal AM62A signal name AM62A Power Domain PMIC open drain signal AM62A signal name AM62A Power Domain PMIC open drain signalAM62A signal nameAM62A Power Domain nINT EXTINTn VDDSHV0 nRSTOUT MCU_PORz VDDS_OSC (1.8V) SCL_I2C1 I2C0_SCL VDDSHV0 SDA_I2C1 I2C0_SDA VDDSHV0 GPIO1 (SCL_I2C2) MCU_I2C0_SCL VDDSHV_MCU GPIO2 (SDA_I2C2) MCU_I2C0_SDA VDDSHV_MCU nINT EXTINTn VDDSHV0 nINTEXTINTnVDDSHV0 nRSTOUT MCU_PORz VDDS_OSC (1.8V) nRSTOUTMCU_PORzVDDS_OSC (1.8V) SCL_I2C1 I2C0_SCL VDDSHV0 SCL_I2C1I2C0_SCLVDDSHV0 SDA_I2C1 I2C0_SDA VDDSHV0 SDA_I2C1I2C0_SDAVDDSHV0 GPIO1 (SCL_I2C2) MCU_I2C0_SCL VDDSHV_MCU GPIO1 (SCL_I2C2)MCU_I2C0_SCLVDDSHV_MCU GPIO2 (SDA_I2C2) MCU_I2C0_SDA VDDSHV_MCU GPIO2 (SDA_I2C2)MCU_I2C0_SDAVDDSHV_MCUPlease use as a guide to understand GPIO assignments required for each PDN system feature. If the feature listed is not required, the digital connection can be removed; however, the GPIO pin is still configured per NVM defined default function shown. After the processor has booted up, the processor can reconfigure unused GPIOs to support new functions. Reconfiguring a GPIO function is possible as long as that function is only needed after boot and default function does not cause any conflicts with normal operations (for example, two outputs driving same net). Digital Connections by System Feature Device GPIO Mapping System Features PMIC Pin NVM Function Active SoC Functional Safety IO + DDR SD Card TPS65931211-Q1 nPWRON/ ENABLE Enable R R INT INT R R nRSTOUT nRSTOUT R SCL_I2C1 SCL_I2C1 R SDA_I2C1 SDA_I2C1 R GPIO_1 SCL_I2C2 R GPIO_2 SDA_I2C2 R GPIO_3 nSLEEP2 R GPIO_4 GPO(enables 3.3V power-switch) R GPIO_5 GPI(sets output voltage on LDO1) O R GPIO_6 GPI(sets output voltage on BUCK1/2/3) R GPIO_7 nERR_MCU R GPIO_8 DISABLE_WDOG O GPIO_9 GPI(enables/disables LDO2) GPIO_10 GPI(sets output voltage on BUCK4) R GPIO_11 GPI(enables/disables LDO1) R Digital Connections by System Feature Device GPIO Mapping System Features PMIC Pin NVM Function Active SoC Functional Safety IO + DDR SD Card TPS65931211-Q1 nPWRON/ ENABLE Enable R R INT INT R R nRSTOUT nRSTOUT R SCL_I2C1 SCL_I2C1 R SDA_I2C1 SDA_I2C1 R GPIO_1 SCL_I2C2 R GPIO_2 SDA_I2C2 R GPIO_3 nSLEEP2 R GPIO_4 GPO(enables 3.3V power-switch) R GPIO_5 GPI(sets output voltage on LDO1) O R GPIO_6 GPI(sets output voltage on BUCK1/2/3) R GPIO_7 nERR_MCU R GPIO_8 DISABLE_WDOG O GPIO_9 GPI(enables/disables LDO2) GPIO_10 GPI(sets output voltage on BUCK4) R GPIO_11 GPI(enables/disables LDO1) R Device GPIO Mapping System Features PMIC Pin NVM Function Active SoC Functional Safety IO + DDR SD Card Device GPIO Mapping System Features DeviceGPIO MappingSystem Features PMIC Pin NVM Function Active SoC Functional Safety IO + DDR SD Card PMIC PinNVM FunctionActive SoCFunctional SafetyIO + DDRSD Card TPS65931211-Q1 nPWRON/ ENABLE Enable R R INT INT R R nRSTOUT nRSTOUT R SCL_I2C1 SCL_I2C1 R SDA_I2C1 SDA_I2C1 R GPIO_1 SCL_I2C2 R GPIO_2 SDA_I2C2 R GPIO_3 nSLEEP2 R GPIO_4 GPO(enables 3.3V power-switch) R GPIO_5 GPI(sets output voltage on LDO1) O R GPIO_6 GPI(sets output voltage on BUCK1/2/3) R GPIO_7 nERR_MCU R GPIO_8 DISABLE_WDOG O GPIO_9 GPI(enables/disables LDO2) GPIO_10 GPI(sets output voltage on BUCK4) R GPIO_11 GPI(enables/disables LDO1) R TPS65931211-Q1 nPWRON/ ENABLE Enable R R TPS65931211-Q1nPWRON/ ENABLEEnableRR INT INT R R INTINTRR nRSTOUT nRSTOUT R nRSTOUTnRSTOUTR SCL_I2C1 SCL_I2C1 R SCL_I2C1SCL_I2C1R SDA_I2C1 SDA_I2C1 R SDA_I2C1SDA_I2C1R GPIO_1 SCL_I2C2 R GPIO_1SCL_I2C2R GPIO_2 SDA_I2C2 R GPIO_2SDA_I2C2R GPIO_3 nSLEEP2 R GPIO_3nSLEEP2R GPIO_4 GPO(enables 3.3V power-switch) R GPIO_4GPO(enables 3.3V power-switch) (enables 3.3V power-switch)R GPIO_5 GPI(sets output voltage on LDO1) O R GPIO_5GPI(sets output voltage on LDO1) (sets output voltage on LDO1)O R GPIO_6 GPI(sets output voltage on BUCK1/2/3) R GPIO_6GPI(sets output voltage on BUCK1/2/3) (sets output voltage on BUCK1/2/3)R GPIO_7 nERR_MCU R GPIO_7nERR_MCUR GPIO_8 DISABLE_WDOG O GPIO_8DISABLE_WDOGO GPIO_9 GPI(enables/disables LDO2) GPIO_9GPI(enables/disables LDO2) (enables/disables LDO2) GPIO_10 GPI(sets output voltage on BUCK4) R GPIO_10GPI(sets output voltage on BUCK4) (sets output voltage on BUCK4)R GPIO_11 GPI(enables/disables LDO1) R GPIO_11GPI(enables/disables LDO1) (enables/disables LDO1)R If it is desired to disable the watchdog through hardware, GPIO_8 is required and must be set high by the time nRSTOUT goes high. After nRSTOUT is high, the watchdog state is latched and the pin can be configured for other functions through software. R is Required. O is optional. GPIO5 from the PMIC does not need to be connected to the processor if LDO1 is not used to supply the uSD card interface. If it is desired to disable the watchdog through hardware, GPIO_8 is required and must be set high by the time nRSTOUT goes high. After nRSTOUT is high, the watchdog state is latched and the pin can be configured for other functions through software.R is Required. O is optional.GPIO5 from the PMIC does not need to be connected to the processor if LDO1 is not used to supply the uSD card interface. Supporting Functional Safety ASIL-B Requirements To achieve a system functional safety level of ASIL-B, the following PDN features are available: PMIC over voltage and under voltage monitoring on the power resource voltage outputs Watchdog monitoring of safety processor MCU error monitoring MCU and Main Domain cold reset I2C communication Error indicator, EN_DRV, for driving external circuitry (optional) Read-back of EN_DRV pin Additional Safety Features PMIC current monitoring on all output power rails Switch short-to-ground detection on BUCK regulator pins (SW_Bx) Read-back of nINT and nRSTOUT logic output pins The PMIC internal over voltage and under voltage monitoring and their respective monitoring threshold levels are enabled by default and can be updated through I2C after startup. PMIC power rails connected directly to the processor are monitored by default. The unused feedback pin of BUCK3 on TPS65931211-Q1, FB_B3, is assigned to monitor the load switch output voltage that supplies the 3.3V I/O domain. A 3.3V supply must be connected to the feedback pin in order to prevent an error since the PMIC is expecting the 3.3V to be present. The internal Q&A Watchdog is enabled on the TPS65931211-Q1 NVM. Once the device is in ACTIVE state, the trigger or Q&A watchdog settings can be configured through the secondary I2C2 (GPIO1/GPIO2) in the device. The primary and secondary I2C CRC is not enabled by default but must be enabled with the I2C_2 trigger described in . Once enabled the secondary I2C is disabled for 2ms. It is recommended to enable I2C CRC and wait a minimum of 2ms before starting the Q&A Watchdog. The steps for configuring and starting the watchdog can be found in the TPS6593-Q1 data sheet. Setting the DISABLE_WDOG signal high disables the watchdog timer if this feature needs to be suspended during initial development or is not required in the system. GPIO_7 of the primary TPS65931211-Q1 PMIC is configured as the MCU error signal monitor, and must be enabled though the ESM_MCU_EN register bit. MCU and Main Domain reset is supported through the connection between the nRSTOUT pin of the PMIC and the MCU_PORz pin of the processor. There is an option to use the EN_DRV to indicate an error has been detected and the system is entering SAFE state. This signal can be utilized if the system has external circuitry that needs to be driven by an error event. In this PDN, the EN_DRV is not utilized, but available if needed. The current monitoring is enabled by default for all BUCKs and LDOs. PMIC System Level Safety Features ASIL-B External SW Wdog INTn Safety MCU Processing ESM Safety MCU Reset Safety Status Signal with IO Read-Back feature System Input Voltage Monitoring PMIC: Q&A Watchdog and I2C2. PMIC: nINT pin connected to EXTINTn on the processor PMIC: nERR_MCU connected to MCU_ERRORn on the processor PMIC: ENDRV VCCA OV/UV is disabled by default but can be enabled by I2C. PMIC Power Monitoring Safety Features Device Power Resource PDN Power Rail ASIL-BSupply Voltage Monitoring TPS65931211-Q1 (PMIC) BUCK1-3 VDD_CORE PMIC - OV & UV BUCK4 VDDS_DDR PMIC - OV & UV BUCK5 DVDD1V8(VDDSHVy) PMIC - OV & UV LDO1 VDDSHV5 PMIC - OV & UVcheck with mike if UV/OV are monitored when LDO is configured as bypass LDO2 VPP (eFUSE) PMIC - OV & UV LDO3 VDDR_CORE PMIC - OV & UV LDO4 VDDA_MCU PMIC - OV & UV TPS22965-Q1 Load Switch DVDD3V3(VDDSHVx) PMIC (FB_B3) - OV & UV Refer to the Safety Manual of the TPS6593-Q1 device for full descriptions and analysis of the PMIC functional safety features. These functional safety features can assist in achieving up to ASIL-B rating for a system. Supporting Functional Safety ASIL-B Requirements To achieve a system functional safety level of ASIL-B, the following PDN features are available: PMIC over voltage and under voltage monitoring on the power resource voltage outputs Watchdog monitoring of safety processor MCU error monitoring MCU and Main Domain cold reset I2C communication Error indicator, EN_DRV, for driving external circuitry (optional) Read-back of EN_DRV pin Additional Safety Features PMIC current monitoring on all output power rails Switch short-to-ground detection on BUCK regulator pins (SW_Bx) Read-back of nINT and nRSTOUT logic output pins The PMIC internal over voltage and under voltage monitoring and their respective monitoring threshold levels are enabled by default and can be updated through I2C after startup. PMIC power rails connected directly to the processor are monitored by default. The unused feedback pin of BUCK3 on TPS65931211-Q1, FB_B3, is assigned to monitor the load switch output voltage that supplies the 3.3V I/O domain. A 3.3V supply must be connected to the feedback pin in order to prevent an error since the PMIC is expecting the 3.3V to be present. The internal Q&A Watchdog is enabled on the TPS65931211-Q1 NVM. Once the device is in ACTIVE state, the trigger or Q&A watchdog settings can be configured through the secondary I2C2 (GPIO1/GPIO2) in the device. The primary and secondary I2C CRC is not enabled by default but must be enabled with the I2C_2 trigger described in . Once enabled the secondary I2C is disabled for 2ms. It is recommended to enable I2C CRC and wait a minimum of 2ms before starting the Q&A Watchdog. The steps for configuring and starting the watchdog can be found in the TPS6593-Q1 data sheet. Setting the DISABLE_WDOG signal high disables the watchdog timer if this feature needs to be suspended during initial development or is not required in the system. GPIO_7 of the primary TPS65931211-Q1 PMIC is configured as the MCU error signal monitor, and must be enabled though the ESM_MCU_EN register bit. MCU and Main Domain reset is supported through the connection between the nRSTOUT pin of the PMIC and the MCU_PORz pin of the processor. There is an option to use the EN_DRV to indicate an error has been detected and the system is entering SAFE state. This signal can be utilized if the system has external circuitry that needs to be driven by an error event. In this PDN, the EN_DRV is not utilized, but available if needed. The current monitoring is enabled by default for all BUCKs and LDOs. PMIC System Level Safety Features ASIL-B External SW Wdog INTn Safety MCU Processing ESM Safety MCU Reset Safety Status Signal with IO Read-Back feature System Input Voltage Monitoring PMIC: Q&A Watchdog and I2C2. PMIC: nINT pin connected to EXTINTn on the processor PMIC: nERR_MCU connected to MCU_ERRORn on the processor PMIC: ENDRV VCCA OV/UV is disabled by default but can be enabled by I2C. PMIC Power Monitoring Safety Features Device Power Resource PDN Power Rail ASIL-BSupply Voltage Monitoring TPS65931211-Q1 (PMIC) BUCK1-3 VDD_CORE PMIC - OV & UV BUCK4 VDDS_DDR PMIC - OV & UV BUCK5 DVDD1V8(VDDSHVy) PMIC - OV & UV LDO1 VDDSHV5 PMIC - OV & UVcheck with mike if UV/OV are monitored when LDO is configured as bypass LDO2 VPP (eFUSE) PMIC - OV & UV LDO3 VDDR_CORE PMIC - OV & UV LDO4 VDDA_MCU PMIC - OV & UV TPS22965-Q1 Load Switch DVDD3V3(VDDSHVx) PMIC (FB_B3) - OV & UV Refer to the Safety Manual of the TPS6593-Q1 device for full descriptions and analysis of the PMIC functional safety features. These functional safety features can assist in achieving up to ASIL-B rating for a system. To achieve a system functional safety level of ASIL-B, the following PDN features are available: PMIC over voltage and under voltage monitoring on the power resource voltage outputs Watchdog monitoring of safety processor MCU error monitoring MCU and Main Domain cold reset I2C communication Error indicator, EN_DRV, for driving external circuitry (optional) Read-back of EN_DRV pin Additional Safety Features PMIC current monitoring on all output power rails Switch short-to-ground detection on BUCK regulator pins (SW_Bx) Read-back of nINT and nRSTOUT logic output pins The PMIC internal over voltage and under voltage monitoring and their respective monitoring threshold levels are enabled by default and can be updated through I2C after startup. PMIC power rails connected directly to the processor are monitored by default. The unused feedback pin of BUCK3 on TPS65931211-Q1, FB_B3, is assigned to monitor the load switch output voltage that supplies the 3.3V I/O domain. A 3.3V supply must be connected to the feedback pin in order to prevent an error since the PMIC is expecting the 3.3V to be present. The internal Q&A Watchdog is enabled on the TPS65931211-Q1 NVM. Once the device is in ACTIVE state, the trigger or Q&A watchdog settings can be configured through the secondary I2C2 (GPIO1/GPIO2) in the device. The primary and secondary I2C CRC is not enabled by default but must be enabled with the I2C_2 trigger described in . Once enabled the secondary I2C is disabled for 2ms. It is recommended to enable I2C CRC and wait a minimum of 2ms before starting the Q&A Watchdog. The steps for configuring and starting the watchdog can be found in the TPS6593-Q1 data sheet. Setting the DISABLE_WDOG signal high disables the watchdog timer if this feature needs to be suspended during initial development or is not required in the system. GPIO_7 of the primary TPS65931211-Q1 PMIC is configured as the MCU error signal monitor, and must be enabled though the ESM_MCU_EN register bit. MCU and Main Domain reset is supported through the connection between the nRSTOUT pin of the PMIC and the MCU_PORz pin of the processor. There is an option to use the EN_DRV to indicate an error has been detected and the system is entering SAFE state. This signal can be utilized if the system has external circuitry that needs to be driven by an error event. In this PDN, the EN_DRV is not utilized, but available if needed. The current monitoring is enabled by default for all BUCKs and LDOs. PMIC System Level Safety Features ASIL-B External SW Wdog INTn Safety MCU Processing ESM Safety MCU Reset Safety Status Signal with IO Read-Back feature System Input Voltage Monitoring PMIC: Q&A Watchdog and I2C2. PMIC: nINT pin connected to EXTINTn on the processor PMIC: nERR_MCU connected to MCU_ERRORn on the processor PMIC: ENDRV VCCA OV/UV is disabled by default but can be enabled by I2C. PMIC Power Monitoring Safety Features Device Power Resource PDN Power Rail ASIL-BSupply Voltage Monitoring TPS65931211-Q1 (PMIC) BUCK1-3 VDD_CORE PMIC - OV & UV BUCK4 VDDS_DDR PMIC - OV & UV BUCK5 DVDD1V8(VDDSHVy) PMIC - OV & UV LDO1 VDDSHV5 PMIC - OV & UVcheck with mike if UV/OV are monitored when LDO is configured as bypass LDO2 VPP (eFUSE) PMIC - OV & UV LDO3 VDDR_CORE PMIC - OV & UV LDO4 VDDA_MCU PMIC - OV & UV TPS22965-Q1 Load Switch DVDD3V3(VDDSHVx) PMIC (FB_B3) - OV & UV Refer to the Safety Manual of the TPS6593-Q1 device for full descriptions and analysis of the PMIC functional safety features. These functional safety features can assist in achieving up to ASIL-B rating for a system. To achieve a system functional safety level of ASIL-B, the following PDN features are available: PMIC over voltage and under voltage monitoring on the power resource voltage outputs Watchdog monitoring of safety processor MCU error monitoring MCU and Main Domain cold reset I2C communication Error indicator, EN_DRV, for driving external circuitry (optional) Read-back of EN_DRV pin PMIC over voltage and under voltage monitoring on the power resource voltage outputs Watchdog monitoring of safety processor MCU error monitoring MCU and Main Domain cold reset I2C communication Error indicator, EN_DRV, for driving external circuitry (optional) Read-back of EN_DRV pin PMIC over voltage and under voltage monitoring on the power resource voltage outputsWatchdog monitoring of safety processorMCU error monitoringMCU and Main Domain cold resetI2C communication2Error indicator, EN_DRV, for driving external circuitry (optional)Read-back of EN_DRV pin Additional Safety Features Additional Safety Features PMIC current monitoring on all output power rails Switch short-to-ground detection on BUCK regulator pins (SW_Bx) Read-back of nINT and nRSTOUT logic output pins PMIC current monitoring on all output power railsSwitch short-to-ground detection on BUCK regulator pins (SW_Bx)Read-back of nINT and nRSTOUT logic output pinsThe PMIC internal over voltage and under voltage monitoring and their respective monitoring threshold levels are enabled by default and can be updated through I2C after startup. PMIC power rails connected directly to the processor are monitored by default. The unused feedback pin of BUCK3 on TPS65931211-Q1, FB_B3, is assigned to monitor the load switch output voltage that supplies the 3.3V I/O domain. A 3.3V supply must be connected to the feedback pin in order to prevent an error since the PMIC is expecting the 3.3V to be present. 2The internal Q&A Watchdog is enabled on the TPS65931211-Q1 NVM. Once the device is in ACTIVE state, the trigger or Q&A watchdog settings can be configured through the secondary I2C2 (GPIO1/GPIO2) in the device. The primary and secondary I2C CRC is not enabled by default but must be enabled with the I2C_2 trigger described in . Once enabled the secondary I2C is disabled for 2ms. It is recommended to enable I2C CRC and wait a minimum of 2ms before starting the Q&A Watchdog. The steps for configuring and starting the watchdog can be found in the TPS6593-Q1 data sheet. Setting the DISABLE_WDOG signal high disables the watchdog timer if this feature needs to be suspended during initial development or is not required in the system. GPIO_7 of the primary TPS65931211-Q1 PMIC is configured as the MCU error signal monitor, and must be enabled though the ESM_MCU_EN register bit. MCU and Main Domain reset is supported through the connection between the nRSTOUT pin of the PMIC and the MCU_PORz pin of the processor. There is an option to use the EN_DRV to indicate an error has been detected and the system is entering SAFE state. This signal can be utilized if the system has external circuitry that needs to be driven by an error event. In this PDN, the EN_DRV is not utilized, but available if needed.The current monitoring is enabled by default for all BUCKs and LDOs. PMIC System Level Safety Features ASIL-B External SW Wdog INTn Safety MCU Processing ESM Safety MCU Reset Safety Status Signal with IO Read-Back feature System Input Voltage Monitoring PMIC: Q&A Watchdog and I2C2. PMIC: nINT pin connected to EXTINTn on the processor PMIC: nERR_MCU connected to MCU_ERRORn on the processor PMIC: ENDRV VCCA OV/UV is disabled by default but can be enabled by I2C. PMIC System Level Safety Features ASIL-B External SW Wdog INTn Safety MCU Processing ESM Safety MCU Reset Safety Status Signal with IO Read-Back feature System Input Voltage Monitoring PMIC: Q&A Watchdog and I2C2. PMIC: nINT pin connected to EXTINTn on the processor PMIC: nERR_MCU connected to MCU_ERRORn on the processor PMIC: ENDRV VCCA OV/UV is disabled by default but can be enabled by I2C. ASIL-B External SW Wdog INTn Safety MCU Processing ESM Safety MCU Reset Safety Status Signal with IO Read-Back feature System Input Voltage Monitoring ASIL-B ASIL-B External SW Wdog INTn Safety MCU Processing ESM Safety MCU Reset Safety Status Signal with IO Read-Back feature System Input Voltage Monitoring External SW Wdog INTn Safety MCU Processing ESM Safety MCU Reset Safety MCU Processing ESM Safety MCU ResetSafety Status Signal with IO Read-Back featureSystem Input Voltage Monitoring PMIC: Q&A Watchdog and I2C2. PMIC: nINT pin connected to EXTINTn on the processor PMIC: nERR_MCU connected to MCU_ERRORn on the processor PMIC: ENDRV VCCA OV/UV is disabled by default but can be enabled by I2C. PMIC: Q&A Watchdog and I2C2. PMIC: nINT pin connected to EXTINTn on the processor PMIC: nERR_MCU connected to MCU_ERRORn on the processor PMIC: ENDRV VCCA OV/UV is disabled by default but can be enabled by I2C. PMIC: Q&A Watchdog and I2C2. PMIC: nINT pin connected to EXTINTn on the processor PMIC: nINT pin connected to EXTINTn on the processor PMIC: nERR_MCU connected to MCU_ERRORn on the processor PMIC: nERR_MCU connected to MCU_ERRORn on the processor PMIC: ENDRVVCCA OV/UV is disabled by default but can be enabled by I2C. PMIC Power Monitoring Safety Features Device Power Resource PDN Power Rail ASIL-BSupply Voltage Monitoring TPS65931211-Q1 (PMIC) BUCK1-3 VDD_CORE PMIC - OV & UV BUCK4 VDDS_DDR PMIC - OV & UV BUCK5 DVDD1V8(VDDSHVy) PMIC - OV & UV LDO1 VDDSHV5 PMIC - OV & UVcheck with mike if UV/OV are monitored when LDO is configured as bypass LDO2 VPP (eFUSE) PMIC - OV & UV LDO3 VDDR_CORE PMIC - OV & UV LDO4 VDDA_MCU PMIC - OV & UV TPS22965-Q1 Load Switch DVDD3V3(VDDSHVx) PMIC (FB_B3) - OV & UV PMIC Power Monitoring Safety Features Device Power Resource PDN Power Rail ASIL-BSupply Voltage Monitoring TPS65931211-Q1 (PMIC) BUCK1-3 VDD_CORE PMIC - OV & UV BUCK4 VDDS_DDR PMIC - OV & UV BUCK5 DVDD1V8(VDDSHVy) PMIC - OV & UV LDO1 VDDSHV5 PMIC - OV & UVcheck with mike if UV/OV are monitored when LDO is configured as bypass LDO2 VPP (eFUSE) PMIC - OV & UV LDO3 VDDR_CORE PMIC - OV & UV LDO4 VDDA_MCU PMIC - OV & UV TPS22965-Q1 Load Switch DVDD3V3(VDDSHVx) PMIC (FB_B3) - OV & UV Device Power Resource PDN Power Rail ASIL-BSupply Voltage Monitoring Device Power Resource PDN Power Rail ASIL-BSupply Voltage Monitoring DevicePower ResourcePDN Power RailASIL-BSupply Voltage Monitoring Supply Voltage Monitoring TPS65931211-Q1 (PMIC) BUCK1-3 VDD_CORE PMIC - OV & UV BUCK4 VDDS_DDR PMIC - OV & UV BUCK5 DVDD1V8(VDDSHVy) PMIC - OV & UV LDO1 VDDSHV5 PMIC - OV & UVcheck with mike if UV/OV are monitored when LDO is configured as bypass LDO2 VPP (eFUSE) PMIC - OV & UV LDO3 VDDR_CORE PMIC - OV & UV LDO4 VDDA_MCU PMIC - OV & UV TPS22965-Q1 Load Switch DVDD3V3(VDDSHVx) PMIC (FB_B3) - OV & UV TPS65931211-Q1 (PMIC) BUCK1-3 VDD_CORE PMIC - OV & UV TPS65931211-Q1 (PMIC)BUCK1-3VDD_COREPMIC - OV & UV BUCK4 VDDS_DDR PMIC - OV & UV BUCK4VDDS_DDRPMIC - OV & UV BUCK5 DVDD1V8(VDDSHVy) PMIC - OV & UV BUCK5DVDD1V8(VDDSHVy)PMIC - OV & UV LDO1 VDDSHV5 PMIC - OV & UVcheck with mike if UV/OV are monitored when LDO is configured as bypass LDO1VDDSHV5PMIC - OV & UVcheck with mike if UV/OV are monitored when LDO is configured as bypass check with mike if UV/OV are monitored when LDO is configured as bypass LDO2 VPP (eFUSE) PMIC - OV & UV LDO2VPP (eFUSE)PMIC - OV & UV LDO3 VDDR_CORE PMIC - OV & UV LDO3VDDR_COREPMIC - OV & UV LDO4 VDDA_MCU PMIC - OV & UV LDO4VDDA_MCUPMIC - OV & UV TPS22965-Q1 Load Switch DVDD3V3(VDDSHVx) PMIC (FB_B3) - OV & UV TPS22965-Q1Load SwitchDVDD3V3(VDDSHVx)PMIC (FB_B3) - OV & UV Refer to the Safety Manual of the TPS6593-Q1 device for full descriptions and analysis of the PMIC functional safety features. These functional safety features can assist in achieving up to ASIL-B rating for a system. Refer to the Safety Manual of the TPS6593-Q1 device for full descriptions and analysis of the PMIC functional safety features. These functional safety features can assist in achieving up to ASIL-B rating for a system. Static NVM Settings The TPS6593-Q1 PMIC consist of user register space and an NVM. The settings in NVM, which are loaded into the user registers during the transition from INIT to BOOT BIST, are provided in this section. Note: The user registers can be changed during state transitions, such as moving from STANDBY to ACTIVE mode. The user register map is described in the TPS6593-Q1 data sheet. Application-Based Configuration Settings In the TPS6593-Q1 data sheet, there are seven application-based configurations for each BUCK to operate within. The following list includes the different configurations available: 2.2 MHz Single Phase for DDR Termination 4.4 MHz VOUT Less than 1.9 V, Multiphase or High COUT Single Phase 4.4 MHz VOUT Less than 1.9 V, Low COUT, Single Phase Only 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only The seven configurations also have optimal output inductance values that optimize the performance of each buck under these various conditions. #GUID-AE4C039E-947C-4D9F-A42B-4A9BC20388AA/T5973073-45 shows the default configurations for the BUCKs. These settings cannot be changed after device startup. Application Use Case Settings Device BUCK Rail Default Application Use Case Recommended Inductor Value TPS65931211-Q1 BUCK1 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK2 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK3 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK4 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK5 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH Device Identification Settings These settings are used to distinguish which device is detected in a system. These settings cannot be changed after device startup. Device Identification NVM Settings Register Name Field Name TPS65931211-Q1 Value Description DEV_REV DEVICE_ID NVM_CODE_1 TI_NVM_ID 0x11 NVM_CODE_2 TI_NVM_REV 0x5 PHASE_CONFIG MP_CONFIG 0x3 3+1+1 BUCK Settings These settings detail the voltages, configurations, and monitoring of the BUCK rails stored in the NVM. All these settings can be changed though I2C after startup. Some settings, typically the enable bits, are also changed by the PFSM, as described in . BUCK NVM Settings Register Name Field Name TPS65931211-Q1 Value Description BUCK1_CTRL BUCK1_EN 0x0 Disabled; BUCK1 regulator BUCK1_FPWM 0x1 PWM operation only. BUCK1_FPWM_MP 0x0 Automatic phase adding and shedding. BUCK1_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK1_VSEL 0x0 BUCK1_VOUT_1 BUCK1_PLDN 0x1 Enabled; Pull-down resistor BUCK1_RV_SEL 0x0 Disabled BUCK1_CONF BUCK1_SLEW_RATE 0x3 5.0 mV/μs BUCK1_ILIM 0x5 5.5 A BUCK2_CTRL BUCK2_EN 0x0 Disabled; BUCK2 regulator BUCK2_FPWM 0x1 PWM operation only. BUCK2_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK2_VSEL 0x0 BUCK2_VOUT_1 BUCK2_PLDN 0x1 Enabled; Pull-down resistor BUCK2_RV_SEL 0x0 Disabled BUCK2_CONF BUCK2_SLEW_RATE 0x3 5.0 mV/μs BUCK2_ILIM 0x5 5.5 A BUCK3_CTRL BUCK3_EN 0x0 Disabled; BUCK3 regulator BUCK3_FPWM 0x1 PWM operation only. BUCK3_FPWM_MP 0x0 Automatic phase adding and shedding. BUCK3_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK3_VSEL 0x0 BUCK3_VOUT_1 BUCK3_PLDN 0x1 Enabled; Pull-down resistor BUCK3_RV_SEL 0x0 Disabled BUCK3_CONF BUCK3_SLEW_RATE 0x0 33 mV/μs BUCK3_ILIM 0x5 5.5 A BUCK4_CTRL BUCK4_EN 0x0 Disabled; BUCK4 regulator BUCK4_FPWM 0x0 PFM and PWM operation (AUTO mode). BUCK4_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK4_VSEL 0x0 BUCK4_VOUT_1 BUCK4_PLDN 0x1 Enabled; Pull-down resistor BUCK4_RV_SEL 0x0 Disabled BUCK4_CONF BUCK4_SLEW_RATE 0x3 5.0 mV/μs BUCK4_ILIM 0x5 5.5 A BUCK5_CTRL BUCK5_EN 0x0 Disabled; BUCK5 regulator BUCK5_FPWM 0x0 PFM and PWM operation (AUTO mode). BUCK5_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK5_VSEL 0x0 BUCK5_VOUT_1 BUCK5_PLDN 0x1 Enable Pull-down resistor BUCK5_RV_SEL 0x0 Disabled BUCK5_CONF BUCK5_SLEW_RATE 0x3 5.0 mV/μs BUCK5_ILIM 0x3 3.5 A BUCK1_VOUT_1 BUCK1_VSET1 0x2d 0.750 V BUCK1_VOUT_2 BUCK1_VSET2 0x2d 0.750 V BUCK2_VOUT_1 BUCK2_VSET1 0x2d 0.750 V BUCK2_VOUT_2 BUCK2_VSET2 0x2d 0.750 V BUCK3_VOUT_1 BUCK3_VSET1 0xfd 3.30 V BUCK3_VOUT_2 BUCK3_VSET2 0xfd 3.30 V BUCK4_VOUT_1 BUCK4_VSET1 0x73 1.10 V BUCK4_VOUT_2 BUCK4_VSET2 0x73 1.10 V BUCK5_VOUT_1 BUCK5_VSET1 0xb2 1.80 V BUCK5_VOUT_2 BUCK5_VSET2 0xb2 1.80 V BUCK1_PG_WINDOW BUCK1_OV_THR 0x3 +5% / +50 mV BUCK1_UV_THR 0x3 -5% / -50 mV BUCK2_PG_WINDOW BUCK2_OV_THR 0x3 +5% / +50 mV BUCK2_UV_THR 0x3 -5% / -50 mV BUCK3_PG_WINDOW BUCK3_OV_THR 0x3 +5% / +50 mV BUCK3_UV_THR 0x3 -5% / -50 mV BUCK4_PG_WINDOW BUCK4_OV_THR 0x4 +6% / +60 mV BUCK4_UV_THR 0x4 -6% / -60 mV BUCK5_PG_WINDOW BUCK5_OV_THR 0x4 +6% / +60 mV BUCK5_UV_THR 0x4 -6% / -60 mV LDO Settings These settings detail the voltages, configurations, and monitoring of the LDO rails stored in the NVM. All these settings can be changed though I2C after startup. Some settings, typically the enable bits, are also changed by the PFSM, as described in . After the sequence has completed, the LDOx_EN and LDOx_VMON_EN bits are set and the LDOx_RV_SEL bit is cleared for all LDOs. The other bits remain unchanged, but are still accessible via I2C. LDO NVM Settings Register Name Field Name TPS65931211-Q1 Value Description LDO1_CTRL LDO1_EN 0x0 Disabled; LDO1 regulator. LDO1_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO1_PLDN 0x1 125 Ohm LDO1_VMON_EN 0x0 Disable OV and UV comparators. LDO1_RV_SEL 0x0 Disabled LDO2_CTRL LDO2_EN 0x0 Disabled; LDO2 regulator. LDO2_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO2_PLDN 0x0 50 kOhm LDO2_VMON_EN 0x0 Disabled; OV and UV comparators. LDO2_RV_SEL 0x0 Disabled LDO3_CTRL LDO3_EN 0x0 Disabled; LDO3 regulator. LDO3_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO3_PLDN 0x1 125 Ohm LDO3_VMON_EN 0x0 Disabled; OV and UV comparators. LDO3_RV_SEL 0x0 Disabled LDO4_CTRL LDO4_EN 0x0 Disabled; LDO4 regulator. LDO4_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO4_PLDN 0x1 125 Ohm LDO4_VMON_EN 0x0 Disabled; OV and UV comparators. LDO4_RV_SEL 0x0 Disabled LDO1_VOUT LDO1_VSET 0x3a 3.30 V LDO1_BYPASS 0x1 Bypass mode. LDO2_VOUT LDO2_VSET 0x1c 1.80 V LDO2_BYPASS 0x0 Linear regulator mode. LDO3_VOUT LDO3_VSET 0x9 0.85 V LDO3_BYPASS 0x0 Linear regulator mode. LDO4_VOUT LDO4_VSET 0x38 1.800 V LDO1_PG_WINDOW LDO1_OV_THR 0x4 +6% / +60 mV LDO1_UV_THR 0x4 -6% / -60 mV LDO2_PG_WINDOW LDO2_OV_THR 0x4 +6% / +60 mV LDO2_UV_THR 0x4 -6% / -60 mV LDO3_PG_WINDOW LDO3_OV_THR 0x4 +6% / +60 mV LDO3_UV_THR 0x4 -6% / -60 mV LDO4_PG_WINDOW LDO4_OV_THR 0x4 +6% / +60 mV LDO4_UV_THR 0x4 -6% / -60 mV VCCA Settings These settings detail the default monitoring enabled on VCCA. All these settings can be changed though I2C after startup. VCCA NVM Settings Register Name Field Name TPS65931211-Q1 Value Description VCCA_VMON_CTRL VMON_DEGLITCH_SEL 0x1 20 us VCCA_VMON_EN 0x0 Disabled; OV and UV comparators. VCCA_PG_WINDOW VCCA_OV_THR 0x7 +10% VCCA_UV_THR 0x7 -10% VCCA_PG_SET 0x1 5.0 V GENERAL_REG_1 FAST_VCCA_OVP 0x0 slow, 4us deglitch filter enabled GENERAL_REG_3 LPM_EN_DISABLES_VCCA_VMON 0x1 VCCA_VMON enabled if VCCA_VMON_EN=1 and LPM_EN=0 GPIO Settings These settings detail the default configurations of the GPIO rails. Note that the contents of the GPIOx_SEL field determine which other fields in the GPIOx_CONF and GPIO_OUT_x registers are applicable. To understand which NVM fields apply to each GPIOx_SEL option, see the Digital Signal Descriptions section in TPS6593-Q1 data sheet. GPIO NVM Settings Register Name Field Name TPS65931211-Q1 Value Description GPIO1_CONF GPIO1_OD 0x0 Push-pull output GPIO1_DIR 0x0 Input GPIO1_SEL 0x1 SCL_I2C2/CS_SPI GPIO1_PU_SEL 0x0 Pull-down resistor selected GPIO1_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor. GPIO1_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO2_CONF GPIO2_OD 0x0 Push-pull output GPIO2_DIR 0x0 Input GPIO2_SEL 0x2 SDA_I2C2/SDO_SPI GPIO2_PU_SEL 0x0 Pull-down resistor selected GPIO2_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor. GPIO2_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO3_CONF GPIO3_OD 0x1 Open-drain output GPIO3_DIR 0x0 Input GPIO3_SEL 0x5 NSLEEP2 GPIO3_PU_SEL 0x0 Pull-down resistor selected GPIO3_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO3_DEGLITCH_EN 0x1 8 us deglitch time. GPIO4_CONF GPIO4_OD 0x0 Push-pull output GPIO4_DIR 0x1 Output GPIO4_SEL 0x0 GPIO4 GPIO4_PU_SEL 0x0 Pull-down resistor selected GPIO4_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor. GPIO4_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO5_CONF GPIO5_OD 0x1 Open-drain output GPIO5_DIR 0x0 Input GPIO5_SEL 0x0 GPIO5 GPIO5_PU_SEL 0x0 Pull-down resistor selected GPIO5_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO5_DEGLITCH_EN 0x1 8 us deglitch time. GPIO6_CONF GPIO6_OD 0x0 Push-pull output GPIO6_DIR 0x0 Input GPIO6_SEL 0x0 GPIO6 GPIO6_PU_SEL 0x0 Pull-down resistor selected GPIO6_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO6_DEGLITCH_EN 0x1 8 us deglitch time. GPIO7_CONF GPIO7_OD 0x1 Open-drain output GPIO7_DIR 0x0 Input GPIO7_SEL 0x1 NERR_MCU GPIO7_PU_SEL 0x0 Pull-down resistor selected GPIO7_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO7_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO8_CONF GPIO8_OD 0x1 Open-drain output GPIO8_DIR 0x0 Input GPIO8_SEL 0x3 DISABLE_WDOG GPIO8_PU_SEL 0x0 Pull-down resistor selected GPIO8_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO8_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO9_CONF GPIO9_OD 0x1 Open-drain output GPIO9_DIR 0x0 Input GPIO9_SEL 0x0 GPIO9 GPIO9_PU_SEL 0x0 Pull-down resistor selected GPIO9_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO9_DEGLITCH_EN 0x1 8 us deglitch time. GPIO10_CONF GPIO10_OD 0x1 Open-drain output GPIO10_DIR 0x0 Input GPIO10_SEL 0x0 GPIO10 GPIO10_PU_SEL 0x0 Pull-down resistor selected GPIO10_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO10_DEGLITCH_EN 0x1 8 us deglitch time. GPIO11_CONF GPIO11_OD 0x1 Open-drain output GPIO11_DIR 0x0 Input GPIO11_SEL 0x0 GPIO11 GPIO11_PU_SEL 0x0 Pull-down resistor selected GPIO11_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO11_DEGLITCH_EN 0x1 8 us deglitch time. NPWRON_CONF NPWRON_SEL 0x0 ENABLE ENABLE_PU_SEL 0x0 Pull-down resistor selected ENABLE_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. ENABLE_DEGLITCH_EN 0x1 8 us deglitch time when ENABLE, 50 ms deglitch time when NPWRON. ENABLE_POL 0x0 Active high NRSTOUT_OD 0x1 Open-drain output GPIO_OUT_1 GPIO1_OUT 0x0 Low GPIO2_OUT 0x0 Low GPIO3_OUT 0x0 Low GPIO4_OUT 0x0 Low GPIO5_OUT 0x0 Low GPIO6_OUT 0x0 Low GPIO7_OUT 0x0 Low GPIO8_OUT 0x0 Low GPIO_OUT_2 GPIO9_OUT 0x0 Low GPIO10_OUT 0x0 Low GPIO11_OUT 0x0 Low Finite State Machine (FSM) Settings These settings describe how the PMIC output rails are assigned to various system-level states. Also, the default trigger for each system-level state is described. All these settings can be changed though I2C after startup. FSM NVM Settings Register Name Field Name TPS65931211-Q1 Value Description RAIL_SEL_1 BUCK1_GRP_SEL 0x1 MCU rail group BUCK2_GRP_SEL 0x1 MCU rail group BUCK3_GRP_SEL 0x1 MCU rail group BUCK4_GRP_SEL 0x1 MCU rail group RAIL_SEL_2 BUCK5_GRP_SEL 0x1 MCU rail group LDO1_GRP_SEL 0x1 MCU rail group LDO2_GRP_SEL 0x3 OTHER rail group LDO3_GRP_SEL 0x1 MCU rail group RAIL_SEL_3 LDO4_GRP_SEL 0x1 MCU rail group VCCA_GRP_SEL 0x0 No group assigned FSM_TRIG_SEL_1 MCU_RAIL_TRIG 0x1 Orderly shutdown SOC_RAIL_TRIG 0x3 SOC power error OTHER_RAIL_TRIG 0x2 MCU power error SEVERE_ERR_TRIG 0x0 Immediate shutdown FSM_TRIG_SEL_2 MODERATE_ERR_TRIG 0x1 Orderly shutdown Interrupt Settings These settings detail the default configurations for what is monitored by nINT pin. All these settings can be changed through I2C after startup. Interrupt NVM Settings Register Name Field Name TPS65931211-Q1 Value Description FSM_TRIG_MASK_1 GPIO1_FSM_MASK 0x1 Masked GPIO1_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO2_FSM_MASK 0x1 Masked GPIO2_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO3_FSM_MASK 0x1 Masked GPIO3_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO4_FSM_MASK 0x1 Masked GPIO4_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' FSM_TRIG_MASK_2 GPIO5_FSM_MASK 0x0 Not masked GPIO5_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO6_FSM_MASK 0x0 Not masked GPIO6_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO7_FSM_MASK 0x1 Masked GPIO7_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO8_FSM_MASK 0x1 Masked GPIO8_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' FSM_TRIG_MASK_3 GPIO9_FSM_MASK 0x0 Not masked GPIO9_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO10_FSM_MASK 0x0 Not masked GPIO10_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO11_FSM_MASK 0x0 Not masked GPIO11_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' MASK_BUCK1_2 BUCK1_ILIM_MASK 0x0 Interrupt generated BUCK1_OV_MASK 0x0 Interrupt generated BUCK1_UV_MASK 0x0 Interrupt generated BUCK2_ILIM_MASK 0x0 Interrupt generated BUCK2_OV_MASK 0x0 Interrupt generated BUCK2_UV_MASK 0x0 Interrupt generated MASK_BUCK3_4 BUCK3_ILIM_MASK 0x0 Interrupt generated BUCK3_OV_MASK 0x0 Interrupt generated BUCK3_UV_MASK 0x0 Interrupt generated BUCK4_OV_MASK 0x0 Interrupt generated BUCK4_UV_MASK 0x0 Interrupt generated BUCK4_ILIM_MASK 0x0 Interrupt generated MASK_BUCK5 BUCK5_ILIM_MASK 0x0 Interrupt generated BUCK5_OV_MASK 0x0 Interrupt generated BUCK5_UV_MASK 0x0 Interrupt generated MASK_LDO1_2 LDO1_OV_MASK 0x0 Interrupt generated LDO1_UV_MASK 0x0 Interrupt generated LDO2_OV_MASK 0x0 Interrupt generated LDO2_UV_MASK 0x0 Interrupt generated LDO1_ILIM_MASK 0x0 Interrupt generated LDO2_ILIM_MASK 0x0 Interrupt generated MASK_LDO3_4 LDO3_OV_MASK 0x0 Interrupt generated LDO3_UV_MASK 0x0 Interrupt generated LDO4_OV_MASK 0x0 Interrupt generated LDO4_UV_MASK 0x0 Interrupt generated LDO3_ILIM_MASK 0x0 Interrupt generated LDO4_ILIM_MASK 0x0 Interrupt generated MASK_VMON VCCA_OV_MASK 0x0 Interrupt generated VCCA_UV_MASK 0x0 Interrupt generated MASK_GPIO1_8_FALL GPIO1_FALL_MASK 0x1 Interrupt not generated. GPIO2_FALL_MASK 0x1 Interrupt not generated. GPIO3_FALL_MASK 0x1 Interrupt not generated. GPIO4_FALL_MASK 0x1 Interrupt not generated. GPIO5_FALL_MASK 0x1 Interrupt not generated. GPIO6_FALL_MASK 0x1 Interrupt not generated. GPIO7_FALL_MASK 0x1 Interrupt not generated. GPIO8_FALL_MASK 0x1 Interrupt not generated. MASK_GPIO1_8_RISE GPIO1_RISE_MASK 0x1 Interrupt not generated. GPIO2_RISE_MASK 0x1 Interrupt not generated. GPIO3_RISE_MASK 0x1 Interrupt not generated. GPIO4_RISE_MASK 0x1 Interrupt not generated. GPIO5_RISE_MASK 0x1 Interrupt not generated. GPIO6_RISE_MASK 0x1 Interrupt not generated. GPIO7_RISE_MASK 0x1 Interrupt not generated. GPIO8_RISE_MASK 0x1 Interrupt not generated. MASK_GPIO9_11 / MASK_GPIO9_10 GPIO9_FALL_MASK 0x1 Interrupt not generated. GPIO9_RISE_MASK 0x1 Interrupt not generated. GPIO10_FALL_MASK 0x1 Interrupt not generated. GPIO11_FALL_MASK 0x1 Interrupt not generated. GPIO10_RISE_MASK 0x1 Interrupt not generated. GPIO11_RISE_MASK 0x1 Interrupt not generated. MASK_STARTUP NPWRON_START_MASK 0x1 Interrupt not generated. ENABLE_MASK 0x0 Interrupt generated FSD_MASK 0x1 Interrupt not generated. SOFT_REBOOT_MASK 0x0 Interrupt generated MASK_MISC TWARN_MASK 0x0 Interrupt generated BIST_PASS_MASK 0x0 Interrupt generated EXT_CLK_MASK 0x1 Interrupt not generated. MASK_MODERATE_ERR BIST_FAIL_MASK 0x0 Interrupt generated REG_CRC_ERR_MASK 0x0 Interrupt generated SPMI_ERR_MASK 0x1 Interrupt not generated. NPWRON_LONG_MASK 0x1 Interrupt not generated. NINT_READBACK_MASK 0x0 Interrupt generated NRSTOUT_READBACK_ MASK 0x0 Interrupt generated MASK_FSM_ERR IMM_SHUTDOWN_MASK 0x0 Interrupt generated MCU_PWR_ERR_MASK 0x0 Interrupt generated SOC_PWR_ERR_MASK 0x0 Interrupt generated ORD_SHUTDOWN_MASK 0x0 Interrupt generated MASK_COMM_ERR COMM_FRM_ERR_MASK 0x1 Interrupt not generated. COMM_CRC_ERR_MASK 0x0 Interrupt generated COMM_ADR_ERR_MASK 0x0 Interrupt generated I2C2_CRC_ERR_MASK 0x0 Interrupt generated I2C2_ADR_ERR_MASK 0x0 Interrupt generated MASK_READBACK_ERR EN_DRV_READBACK_ MASK 0x0 Interrupt generated NRSTOUT_SOC_ READBACK_MASK 0x1 Interrupt not generated. MASK_ESM ESM_SOC_PIN_MASK 0x1 Interrupt not generated. ESM_SOC_RST_MASK 0x1 Interrupt not generated. ESM_SOC_FAIL_MASK 0x1 Interrupt not generated. ESM_MCU_PIN_MASK 0x0 Interrupt generated ESM_MCU_RST_MASK 0x0 Interrupt generated ESM_MCU_FAIL_MASK 0x0 Interrupt generated GENERAL_REG_1 PFSM_ERR_MASK 0x0 Interrupt generated POWERGOOD Settings These settings detail the default configurations for what is monitored by PGOOD pin. All these settings can be changed though I2C after startup. POWERGOOD NVM Settings Register Name Field Name TPS65931211-Q1 Value Description PGOOD_SEL_1 PGOOD_SEL_BUCK1 0x1 Voltage only PGOOD_SEL_BUCK2 0x1 Voltage only PGOOD_SEL_BUCK3 0x1 Voltage only PGOOD_SEL_BUCK4 0x1 Voltage only PGOOD_SEL_2 PGOOD_SEL_BUCK5 0x1 Voltage only PGOOD_SEL_3 PGOOD_SEL_LDO1 0x1 Voltage only PGOOD_SEL_LDO2 0x1 Voltage only PGOOD_SEL_LDO3 0x1 Voltage only PGOOD_SEL_LDO4 0x1 Voltage only PGOOD_SEL_4 PGOOD_SEL_VCCA 0x1 VCCA OV/UV threshold affecting PGOOD signal PGOOD_SEL_TDIE_WARN 0x1 Thermal warning affecting to PGOOD signal PGOOD_SEL_NRSTOUT 0x1 nRSTOUT pin low state forces PGOOD signal to low PGOOD_SEL_NRSTOUT_ SOC 0x0 Masked PGOOD_POL 0x0 PGOOD signal is high when monitored inputs are valid PGOOD_WINDOW 0x1 Both undervoltage and overvoltage are monitored Miscellaneous Settings These settings detail the default configurations of additional settings, such as spread spectrum, BUCK frequency, and LDO timeout. All these settings can be changed though I2C after startup. Miscellaneous NVM Settings Register Name Field Name TPS65931211-Q1 Value Description PLL_CTRL EXT_CLK_FREQ 0x0 1.1 MHz CONFIG_1 TWARN_LEVEL 0x1 140C I2C1_HS 0x0 Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode primary code. I2C2_HS 0x0 Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode primary code. EN_ILIM_FSM_CTRL 0x0 Buck/LDO regulators ILIM interrupts do not affect FSM triggers. NSLEEP1_MASK 0x1 NSLEEP1(B) does not affect FSM state transitions. NSLEEP2_MASK 0x0 NSLEEP2(B) affects FSM state transitions. CONFIG_2 BB_CHARGER_EN 0x0 Disabled BB_VEOC 0x0 2.5V BB_ICHR 0x0 100uA RECOV_CNT_REG_2 RECOV_CNT_THR 0xf 0xf BUCK_RESET_REG BUCK1_RESET 0x0 0x0 BUCK2_RESET 0x0 0x0 BUCK3_RESET 0x0 0x0 BUCK4_RESET 0x0 0x0 BUCK5_RESET 0x0 0x0 SPREAD_SPECTRUM_1 SS_EN 0x0 Spread spectrum disabled SS_MODE 0x1 Mixed dwell SS_DEPTH 0x0 No modulation SPREAD_SPECTRUM_2 SS_PARAM1 0x7 0x7 SS_PARAM2 0xc 0xc FREQ_SEL BUCK1_FREQ_SEL 0x0 2.2 MHz BUCK2_FREQ_SEL 0x0 2.2 MHz BUCK3_FREQ_SEL 0x0 2.2 MHz BUCK4_FREQ_SEL 0x0 2.2 MHz BUCK5_FREQ_SEL 0x0 2.2 MHz FSM_STEP_SIZE PFSM_DELAY_STEP 0xb 0xb LDO_RV_TIMEOUT_ REG_1 LDO1_RV_TIMEOUT 0xf 16ms LDO2_RV_TIMEOUT 0xf 16ms LDO_RV_TIMEOUT_ REG_2 LDO3_RV_TIMEOUT 0xf 16ms LDO4_RV_TIMEOUT 0xf 16ms USER_SPARE_REGS USER_SPARE_1 0x0 0x0 USER_SPARE_2 0x0 0x0 USER_SPARE_3 0x0 0x0 USER_SPARE_4 0x0 0x0 ESM_MCU_MODE_ CFG ESM_MCU_EN 0x0 ESM_MCU disabled. ESM_SOC_MODE_ CFG ESM_SOC_EN 0x0 ESM_SoC disabled. CUSTOMER_NVM_ID_REG CUSTOMER_NVM_ID 0x0 0x0 RTC_CTRL_2 XTAL_EN 0x0 Crystal oscillator is disabled LP_STANDBY_SEL 0x0 LDOINT is enabled in standby state. FAST_BIST 0x0 Logic and analog BIST is run at BOOT BIST. STARTUP_DEST 0x3 ACTIVE XTAL_SEL 0x0 6 pF PFSM_DELAY_REG_1 PFSM_DELAY1 0x0 0x0 PFSM_DELAY_REG_2 PFSM_DELAY2 0x0 0x0 PFSM_DELAY_REG_3 PFSM_DELAY3 0x0 0x0 PFSM_DELAY_REG_4 PFSM_DELAY4 0x0 0x0 GENERAL_REG_0 FAST_BOOT_BIST 0x0 LBIST is run during boot BIST GENERAL_REG_1 REG_CRC_EN 0x0 Register CRC disabled Interface Settings These settings detail the default interface, interface configurations, and device addresses. These settings cannot be changed after device startup. Interface NVM Settings Register Name Field Name TPS65931211-Q1 Value Description SERIAL_IF_CONFIG I2C_SPI_SEL 0x0 I2C I2C1_SPI_CRC_EN 0x0 CRC disabled I2C2_CRC_EN 0x0 CRC disabled I2C1_ID_REG I2C1_ID 0x48 0x48 I2C2_ID_REG I2C2_ID 0x12 0x12 Watchdog Settings These settings detail the default watchdog addresses. These settings can be changed though I2C after startup. Watchdog NVM Settings Register Name Field Name TPS65931211-Q1 Value Description WD_LONGWIN_CFG WD_LONGWIN 0xff 0xff WD_THR_CFG WD_EN 0x1 Watchdog enabled. Static NVM Settings The TPS6593-Q1 PMIC consist of user register space and an NVM. The settings in NVM, which are loaded into the user registers during the transition from INIT to BOOT BIST, are provided in this section. Note: The user registers can be changed during state transitions, such as moving from STANDBY to ACTIVE mode. The user register map is described in the TPS6593-Q1 data sheet. The TPS6593-Q1 PMIC consist of user register space and an NVM. The settings in NVM, which are loaded into the user registers during the transition from INIT to BOOT BIST, are provided in this section. Note: The user registers can be changed during state transitions, such as moving from STANDBY to ACTIVE mode. The user register map is described in the TPS6593-Q1 data sheet. The TPS6593-Q1 PMIC consist of user register space and an NVM. The settings in NVM, which are loaded into the user registers during the transition from INIT to BOOT BIST, are provided in this section. Note: The user registers can be changed during state transitions, such as moving from STANDBY to ACTIVE mode. The user register map is described in the TPS6593-Q1 data sheet. Application-Based Configuration Settings In the TPS6593-Q1 data sheet, there are seven application-based configurations for each BUCK to operate within. The following list includes the different configurations available: 2.2 MHz Single Phase for DDR Termination 4.4 MHz VOUT Less than 1.9 V, Multiphase or High COUT Single Phase 4.4 MHz VOUT Less than 1.9 V, Low COUT, Single Phase Only 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only The seven configurations also have optimal output inductance values that optimize the performance of each buck under these various conditions. #GUID-AE4C039E-947C-4D9F-A42B-4A9BC20388AA/T5973073-45 shows the default configurations for the BUCKs. These settings cannot be changed after device startup. Application Use Case Settings Device BUCK Rail Default Application Use Case Recommended Inductor Value TPS65931211-Q1 BUCK1 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK2 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK3 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK4 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK5 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH Application-Based Configuration Settings In the TPS6593-Q1 data sheet, there are seven application-based configurations for each BUCK to operate within. The following list includes the different configurations available: 2.2 MHz Single Phase for DDR Termination 4.4 MHz VOUT Less than 1.9 V, Multiphase or High COUT Single Phase 4.4 MHz VOUT Less than 1.9 V, Low COUT, Single Phase Only 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only The seven configurations also have optimal output inductance values that optimize the performance of each buck under these various conditions. #GUID-AE4C039E-947C-4D9F-A42B-4A9BC20388AA/T5973073-45 shows the default configurations for the BUCKs. These settings cannot be changed after device startup. Application Use Case Settings Device BUCK Rail Default Application Use Case Recommended Inductor Value TPS65931211-Q1 BUCK1 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK2 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK3 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK4 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK5 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH In the TPS6593-Q1 data sheet, there are seven application-based configurations for each BUCK to operate within. The following list includes the different configurations available: 2.2 MHz Single Phase for DDR Termination 4.4 MHz VOUT Less than 1.9 V, Multiphase or High COUT Single Phase 4.4 MHz VOUT Less than 1.9 V, Low COUT, Single Phase Only 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only The seven configurations also have optimal output inductance values that optimize the performance of each buck under these various conditions. #GUID-AE4C039E-947C-4D9F-A42B-4A9BC20388AA/T5973073-45 shows the default configurations for the BUCKs. These settings cannot be changed after device startup. Application Use Case Settings Device BUCK Rail Default Application Use Case Recommended Inductor Value TPS65931211-Q1 BUCK1 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK2 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK3 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK4 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK5 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH In the TPS6593-Q1 data sheet, there are seven application-based configurations for each BUCK to operate within. The following list includes the different configurations available: 2.2 MHz Single Phase for DDR Termination 4.4 MHz VOUT Less than 1.9 V, Multiphase or High COUT Single Phase 4.4 MHz VOUT Less than 1.9 V, Low COUT, Single Phase Only 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only 2.2 MHz Single Phase for DDR Termination 4.4 MHz VOUT Less than 1.9 V, Multiphase or High COUT Single Phase 4.4 MHz VOUT Less than 1.9 V, Low COUT, Single Phase Only 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only 2.2 MHz Single Phase for DDR Termination4.4 MHz VOUT Less than 1.9 V, Multiphase or High COUT Single Phase4.4 MHz VOUT Less than 1.9 V, Low COUT, Single Phase Only4.4 MHz VOUT Greater than 1.7 V, Single Phase Only2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only2.2 MHz Full VOUT and Full VIN Range, Single Phase OnlyThe seven configurations also have optimal output inductance values that optimize the performance of each buck under these various conditions. #GUID-AE4C039E-947C-4D9F-A42B-4A9BC20388AA/T5973073-45 shows the default configurations for the BUCKs. These settings cannot be changed after device startup.#GUID-AE4C039E-947C-4D9F-A42B-4A9BC20388AA/T5973073-45 Application Use Case Settings Device BUCK Rail Default Application Use Case Recommended Inductor Value TPS65931211-Q1 BUCK1 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK2 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK3 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK4 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK5 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH Application Use Case Settings Device BUCK Rail Default Application Use Case Recommended Inductor Value TPS65931211-Q1 BUCK1 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK2 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK3 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK4 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK5 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH Device BUCK Rail Default Application Use Case Recommended Inductor Value Device BUCK Rail Default Application Use Case Recommended Inductor Value DeviceBUCK RailDefault Application Use CaseRecommended Inductor Value TPS65931211-Q1 BUCK1 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK2 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK3 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK4 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK5 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH TPS65931211-Q1 BUCK1 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH TPS65931211-Q1BUCK12.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase470 nH BUCK2 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK22.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase470 nH BUCK3 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK32.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase470 nH BUCK4 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK42.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase470 nH BUCK5 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH BUCK52.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase470 nH Device Identification Settings These settings are used to distinguish which device is detected in a system. These settings cannot be changed after device startup. Device Identification NVM Settings Register Name Field Name TPS65931211-Q1 Value Description DEV_REV DEVICE_ID NVM_CODE_1 TI_NVM_ID 0x11 NVM_CODE_2 TI_NVM_REV 0x5 PHASE_CONFIG MP_CONFIG 0x3 3+1+1 Device Identification Settings These settings are used to distinguish which device is detected in a system. These settings cannot be changed after device startup. Device Identification NVM Settings Register Name Field Name TPS65931211-Q1 Value Description DEV_REV DEVICE_ID NVM_CODE_1 TI_NVM_ID 0x11 NVM_CODE_2 TI_NVM_REV 0x5 PHASE_CONFIG MP_CONFIG 0x3 3+1+1 These settings are used to distinguish which device is detected in a system. These settings cannot be changed after device startup. Device Identification NVM Settings Register Name Field Name TPS65931211-Q1 Value Description DEV_REV DEVICE_ID NVM_CODE_1 TI_NVM_ID 0x11 NVM_CODE_2 TI_NVM_REV 0x5 PHASE_CONFIG MP_CONFIG 0x3 3+1+1 These settings are used to distinguish which device is detected in a system. These settings cannot be changed after device startup. Device Identification NVM Settings Register Name Field Name TPS65931211-Q1 Value Description DEV_REV DEVICE_ID NVM_CODE_1 TI_NVM_ID 0x11 NVM_CODE_2 TI_NVM_REV 0x5 PHASE_CONFIG MP_CONFIG 0x3 3+1+1 Device Identification NVM Settings Register Name Field Name TPS65931211-Q1 Value Description DEV_REV DEVICE_ID NVM_CODE_1 TI_NVM_ID 0x11 NVM_CODE_2 TI_NVM_REV 0x5 PHASE_CONFIG MP_CONFIG 0x3 3+1+1 Register Name Field Name TPS65931211-Q1 Value Description Register Name Field Name TPS65931211-Q1 Register NameField Name TPS65931211-Q1 TPS65931211-Q1 Value Description ValueDescription DEV_REV DEVICE_ID NVM_CODE_1 TI_NVM_ID 0x11 NVM_CODE_2 TI_NVM_REV 0x5 PHASE_CONFIG MP_CONFIG 0x3 3+1+1 DEV_REV DEVICE_ID DEV_REVDEVICE_ID NVM_CODE_1 TI_NVM_ID 0x11 NVM_CODE_1TI_NVM_ID 0x11 0x11 NVM_CODE_2 TI_NVM_REV 0x5 NVM_CODE_2TI_NVM_REV 0x5 0x5 PHASE_CONFIG MP_CONFIG 0x3 3+1+1 PHASE_CONFIGMP_CONFIG 0x3 0x3 3+1+1 3+1+1 BUCK Settings These settings detail the voltages, configurations, and monitoring of the BUCK rails stored in the NVM. All these settings can be changed though I2C after startup. Some settings, typically the enable bits, are also changed by the PFSM, as described in . BUCK NVM Settings Register Name Field Name TPS65931211-Q1 Value Description BUCK1_CTRL BUCK1_EN 0x0 Disabled; BUCK1 regulator BUCK1_FPWM 0x1 PWM operation only. BUCK1_FPWM_MP 0x0 Automatic phase adding and shedding. BUCK1_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK1_VSEL 0x0 BUCK1_VOUT_1 BUCK1_PLDN 0x1 Enabled; Pull-down resistor BUCK1_RV_SEL 0x0 Disabled BUCK1_CONF BUCK1_SLEW_RATE 0x3 5.0 mV/μs BUCK1_ILIM 0x5 5.5 A BUCK2_CTRL BUCK2_EN 0x0 Disabled; BUCK2 regulator BUCK2_FPWM 0x1 PWM operation only. BUCK2_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK2_VSEL 0x0 BUCK2_VOUT_1 BUCK2_PLDN 0x1 Enabled; Pull-down resistor BUCK2_RV_SEL 0x0 Disabled BUCK2_CONF BUCK2_SLEW_RATE 0x3 5.0 mV/μs BUCK2_ILIM 0x5 5.5 A BUCK3_CTRL BUCK3_EN 0x0 Disabled; BUCK3 regulator BUCK3_FPWM 0x1 PWM operation only. BUCK3_FPWM_MP 0x0 Automatic phase adding and shedding. BUCK3_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK3_VSEL 0x0 BUCK3_VOUT_1 BUCK3_PLDN 0x1 Enabled; Pull-down resistor BUCK3_RV_SEL 0x0 Disabled BUCK3_CONF BUCK3_SLEW_RATE 0x0 33 mV/μs BUCK3_ILIM 0x5 5.5 A BUCK4_CTRL BUCK4_EN 0x0 Disabled; BUCK4 regulator BUCK4_FPWM 0x0 PFM and PWM operation (AUTO mode). BUCK4_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK4_VSEL 0x0 BUCK4_VOUT_1 BUCK4_PLDN 0x1 Enabled; Pull-down resistor BUCK4_RV_SEL 0x0 Disabled BUCK4_CONF BUCK4_SLEW_RATE 0x3 5.0 mV/μs BUCK4_ILIM 0x5 5.5 A BUCK5_CTRL BUCK5_EN 0x0 Disabled; BUCK5 regulator BUCK5_FPWM 0x0 PFM and PWM operation (AUTO mode). BUCK5_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK5_VSEL 0x0 BUCK5_VOUT_1 BUCK5_PLDN 0x1 Enable Pull-down resistor BUCK5_RV_SEL 0x0 Disabled BUCK5_CONF BUCK5_SLEW_RATE 0x3 5.0 mV/μs BUCK5_ILIM 0x3 3.5 A BUCK1_VOUT_1 BUCK1_VSET1 0x2d 0.750 V BUCK1_VOUT_2 BUCK1_VSET2 0x2d 0.750 V BUCK2_VOUT_1 BUCK2_VSET1 0x2d 0.750 V BUCK2_VOUT_2 BUCK2_VSET2 0x2d 0.750 V BUCK3_VOUT_1 BUCK3_VSET1 0xfd 3.30 V BUCK3_VOUT_2 BUCK3_VSET2 0xfd 3.30 V BUCK4_VOUT_1 BUCK4_VSET1 0x73 1.10 V BUCK4_VOUT_2 BUCK4_VSET2 0x73 1.10 V BUCK5_VOUT_1 BUCK5_VSET1 0xb2 1.80 V BUCK5_VOUT_2 BUCK5_VSET2 0xb2 1.80 V BUCK1_PG_WINDOW BUCK1_OV_THR 0x3 +5% / +50 mV BUCK1_UV_THR 0x3 -5% / -50 mV BUCK2_PG_WINDOW BUCK2_OV_THR 0x3 +5% / +50 mV BUCK2_UV_THR 0x3 -5% / -50 mV BUCK3_PG_WINDOW BUCK3_OV_THR 0x3 +5% / +50 mV BUCK3_UV_THR 0x3 -5% / -50 mV BUCK4_PG_WINDOW BUCK4_OV_THR 0x4 +6% / +60 mV BUCK4_UV_THR 0x4 -6% / -60 mV BUCK5_PG_WINDOW BUCK5_OV_THR 0x4 +6% / +60 mV BUCK5_UV_THR 0x4 -6% / -60 mV BUCK Settings These settings detail the voltages, configurations, and monitoring of the BUCK rails stored in the NVM. All these settings can be changed though I2C after startup. Some settings, typically the enable bits, are also changed by the PFSM, as described in . BUCK NVM Settings Register Name Field Name TPS65931211-Q1 Value Description BUCK1_CTRL BUCK1_EN 0x0 Disabled; BUCK1 regulator BUCK1_FPWM 0x1 PWM operation only. BUCK1_FPWM_MP 0x0 Automatic phase adding and shedding. BUCK1_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK1_VSEL 0x0 BUCK1_VOUT_1 BUCK1_PLDN 0x1 Enabled; Pull-down resistor BUCK1_RV_SEL 0x0 Disabled BUCK1_CONF BUCK1_SLEW_RATE 0x3 5.0 mV/μs BUCK1_ILIM 0x5 5.5 A BUCK2_CTRL BUCK2_EN 0x0 Disabled; BUCK2 regulator BUCK2_FPWM 0x1 PWM operation only. BUCK2_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK2_VSEL 0x0 BUCK2_VOUT_1 BUCK2_PLDN 0x1 Enabled; Pull-down resistor BUCK2_RV_SEL 0x0 Disabled BUCK2_CONF BUCK2_SLEW_RATE 0x3 5.0 mV/μs BUCK2_ILIM 0x5 5.5 A BUCK3_CTRL BUCK3_EN 0x0 Disabled; BUCK3 regulator BUCK3_FPWM 0x1 PWM operation only. BUCK3_FPWM_MP 0x0 Automatic phase adding and shedding. BUCK3_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK3_VSEL 0x0 BUCK3_VOUT_1 BUCK3_PLDN 0x1 Enabled; Pull-down resistor BUCK3_RV_SEL 0x0 Disabled BUCK3_CONF BUCK3_SLEW_RATE 0x0 33 mV/μs BUCK3_ILIM 0x5 5.5 A BUCK4_CTRL BUCK4_EN 0x0 Disabled; BUCK4 regulator BUCK4_FPWM 0x0 PFM and PWM operation (AUTO mode). BUCK4_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK4_VSEL 0x0 BUCK4_VOUT_1 BUCK4_PLDN 0x1 Enabled; Pull-down resistor BUCK4_RV_SEL 0x0 Disabled BUCK4_CONF BUCK4_SLEW_RATE 0x3 5.0 mV/μs BUCK4_ILIM 0x5 5.5 A BUCK5_CTRL BUCK5_EN 0x0 Disabled; BUCK5 regulator BUCK5_FPWM 0x0 PFM and PWM operation (AUTO mode). BUCK5_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK5_VSEL 0x0 BUCK5_VOUT_1 BUCK5_PLDN 0x1 Enable Pull-down resistor BUCK5_RV_SEL 0x0 Disabled BUCK5_CONF BUCK5_SLEW_RATE 0x3 5.0 mV/μs BUCK5_ILIM 0x3 3.5 A BUCK1_VOUT_1 BUCK1_VSET1 0x2d 0.750 V BUCK1_VOUT_2 BUCK1_VSET2 0x2d 0.750 V BUCK2_VOUT_1 BUCK2_VSET1 0x2d 0.750 V BUCK2_VOUT_2 BUCK2_VSET2 0x2d 0.750 V BUCK3_VOUT_1 BUCK3_VSET1 0xfd 3.30 V BUCK3_VOUT_2 BUCK3_VSET2 0xfd 3.30 V BUCK4_VOUT_1 BUCK4_VSET1 0x73 1.10 V BUCK4_VOUT_2 BUCK4_VSET2 0x73 1.10 V BUCK5_VOUT_1 BUCK5_VSET1 0xb2 1.80 V BUCK5_VOUT_2 BUCK5_VSET2 0xb2 1.80 V BUCK1_PG_WINDOW BUCK1_OV_THR 0x3 +5% / +50 mV BUCK1_UV_THR 0x3 -5% / -50 mV BUCK2_PG_WINDOW BUCK2_OV_THR 0x3 +5% / +50 mV BUCK2_UV_THR 0x3 -5% / -50 mV BUCK3_PG_WINDOW BUCK3_OV_THR 0x3 +5% / +50 mV BUCK3_UV_THR 0x3 -5% / -50 mV BUCK4_PG_WINDOW BUCK4_OV_THR 0x4 +6% / +60 mV BUCK4_UV_THR 0x4 -6% / -60 mV BUCK5_PG_WINDOW BUCK5_OV_THR 0x4 +6% / +60 mV BUCK5_UV_THR 0x4 -6% / -60 mV These settings detail the voltages, configurations, and monitoring of the BUCK rails stored in the NVM. All these settings can be changed though I2C after startup. Some settings, typically the enable bits, are also changed by the PFSM, as described in . BUCK NVM Settings Register Name Field Name TPS65931211-Q1 Value Description BUCK1_CTRL BUCK1_EN 0x0 Disabled; BUCK1 regulator BUCK1_FPWM 0x1 PWM operation only. BUCK1_FPWM_MP 0x0 Automatic phase adding and shedding. BUCK1_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK1_VSEL 0x0 BUCK1_VOUT_1 BUCK1_PLDN 0x1 Enabled; Pull-down resistor BUCK1_RV_SEL 0x0 Disabled BUCK1_CONF BUCK1_SLEW_RATE 0x3 5.0 mV/μs BUCK1_ILIM 0x5 5.5 A BUCK2_CTRL BUCK2_EN 0x0 Disabled; BUCK2 regulator BUCK2_FPWM 0x1 PWM operation only. BUCK2_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK2_VSEL 0x0 BUCK2_VOUT_1 BUCK2_PLDN 0x1 Enabled; Pull-down resistor BUCK2_RV_SEL 0x0 Disabled BUCK2_CONF BUCK2_SLEW_RATE 0x3 5.0 mV/μs BUCK2_ILIM 0x5 5.5 A BUCK3_CTRL BUCK3_EN 0x0 Disabled; BUCK3 regulator BUCK3_FPWM 0x1 PWM operation only. BUCK3_FPWM_MP 0x0 Automatic phase adding and shedding. BUCK3_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK3_VSEL 0x0 BUCK3_VOUT_1 BUCK3_PLDN 0x1 Enabled; Pull-down resistor BUCK3_RV_SEL 0x0 Disabled BUCK3_CONF BUCK3_SLEW_RATE 0x0 33 mV/μs BUCK3_ILIM 0x5 5.5 A BUCK4_CTRL BUCK4_EN 0x0 Disabled; BUCK4 regulator BUCK4_FPWM 0x0 PFM and PWM operation (AUTO mode). BUCK4_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK4_VSEL 0x0 BUCK4_VOUT_1 BUCK4_PLDN 0x1 Enabled; Pull-down resistor BUCK4_RV_SEL 0x0 Disabled BUCK4_CONF BUCK4_SLEW_RATE 0x3 5.0 mV/μs BUCK4_ILIM 0x5 5.5 A BUCK5_CTRL BUCK5_EN 0x0 Disabled; BUCK5 regulator BUCK5_FPWM 0x0 PFM and PWM operation (AUTO mode). BUCK5_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK5_VSEL 0x0 BUCK5_VOUT_1 BUCK5_PLDN 0x1 Enable Pull-down resistor BUCK5_RV_SEL 0x0 Disabled BUCK5_CONF BUCK5_SLEW_RATE 0x3 5.0 mV/μs BUCK5_ILIM 0x3 3.5 A BUCK1_VOUT_1 BUCK1_VSET1 0x2d 0.750 V BUCK1_VOUT_2 BUCK1_VSET2 0x2d 0.750 V BUCK2_VOUT_1 BUCK2_VSET1 0x2d 0.750 V BUCK2_VOUT_2 BUCK2_VSET2 0x2d 0.750 V BUCK3_VOUT_1 BUCK3_VSET1 0xfd 3.30 V BUCK3_VOUT_2 BUCK3_VSET2 0xfd 3.30 V BUCK4_VOUT_1 BUCK4_VSET1 0x73 1.10 V BUCK4_VOUT_2 BUCK4_VSET2 0x73 1.10 V BUCK5_VOUT_1 BUCK5_VSET1 0xb2 1.80 V BUCK5_VOUT_2 BUCK5_VSET2 0xb2 1.80 V BUCK1_PG_WINDOW BUCK1_OV_THR 0x3 +5% / +50 mV BUCK1_UV_THR 0x3 -5% / -50 mV BUCK2_PG_WINDOW BUCK2_OV_THR 0x3 +5% / +50 mV BUCK2_UV_THR 0x3 -5% / -50 mV BUCK3_PG_WINDOW BUCK3_OV_THR 0x3 +5% / +50 mV BUCK3_UV_THR 0x3 -5% / -50 mV BUCK4_PG_WINDOW BUCK4_OV_THR 0x4 +6% / +60 mV BUCK4_UV_THR 0x4 -6% / -60 mV BUCK5_PG_WINDOW BUCK5_OV_THR 0x4 +6% / +60 mV BUCK5_UV_THR 0x4 -6% / -60 mV These settings detail the voltages, configurations, and monitoring of the BUCK rails stored in the NVM. All these settings can be changed though I2C after startup. Some settings, typically the enable bits, are also changed by the PFSM, as described in .2 BUCK NVM Settings Register Name Field Name TPS65931211-Q1 Value Description BUCK1_CTRL BUCK1_EN 0x0 Disabled; BUCK1 regulator BUCK1_FPWM 0x1 PWM operation only. BUCK1_FPWM_MP 0x0 Automatic phase adding and shedding. BUCK1_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK1_VSEL 0x0 BUCK1_VOUT_1 BUCK1_PLDN 0x1 Enabled; Pull-down resistor BUCK1_RV_SEL 0x0 Disabled BUCK1_CONF BUCK1_SLEW_RATE 0x3 5.0 mV/μs BUCK1_ILIM 0x5 5.5 A BUCK2_CTRL BUCK2_EN 0x0 Disabled; BUCK2 regulator BUCK2_FPWM 0x1 PWM operation only. BUCK2_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK2_VSEL 0x0 BUCK2_VOUT_1 BUCK2_PLDN 0x1 Enabled; Pull-down resistor BUCK2_RV_SEL 0x0 Disabled BUCK2_CONF BUCK2_SLEW_RATE 0x3 5.0 mV/μs BUCK2_ILIM 0x5 5.5 A BUCK3_CTRL BUCK3_EN 0x0 Disabled; BUCK3 regulator BUCK3_FPWM 0x1 PWM operation only. BUCK3_FPWM_MP 0x0 Automatic phase adding and shedding. BUCK3_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK3_VSEL 0x0 BUCK3_VOUT_1 BUCK3_PLDN 0x1 Enabled; Pull-down resistor BUCK3_RV_SEL 0x0 Disabled BUCK3_CONF BUCK3_SLEW_RATE 0x0 33 mV/μs BUCK3_ILIM 0x5 5.5 A BUCK4_CTRL BUCK4_EN 0x0 Disabled; BUCK4 regulator BUCK4_FPWM 0x0 PFM and PWM operation (AUTO mode). BUCK4_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK4_VSEL 0x0 BUCK4_VOUT_1 BUCK4_PLDN 0x1 Enabled; Pull-down resistor BUCK4_RV_SEL 0x0 Disabled BUCK4_CONF BUCK4_SLEW_RATE 0x3 5.0 mV/μs BUCK4_ILIM 0x5 5.5 A BUCK5_CTRL BUCK5_EN 0x0 Disabled; BUCK5 regulator BUCK5_FPWM 0x0 PFM and PWM operation (AUTO mode). BUCK5_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK5_VSEL 0x0 BUCK5_VOUT_1 BUCK5_PLDN 0x1 Enable Pull-down resistor BUCK5_RV_SEL 0x0 Disabled BUCK5_CONF BUCK5_SLEW_RATE 0x3 5.0 mV/μs BUCK5_ILIM 0x3 3.5 A BUCK1_VOUT_1 BUCK1_VSET1 0x2d 0.750 V BUCK1_VOUT_2 BUCK1_VSET2 0x2d 0.750 V BUCK2_VOUT_1 BUCK2_VSET1 0x2d 0.750 V BUCK2_VOUT_2 BUCK2_VSET2 0x2d 0.750 V BUCK3_VOUT_1 BUCK3_VSET1 0xfd 3.30 V BUCK3_VOUT_2 BUCK3_VSET2 0xfd 3.30 V BUCK4_VOUT_1 BUCK4_VSET1 0x73 1.10 V BUCK4_VOUT_2 BUCK4_VSET2 0x73 1.10 V BUCK5_VOUT_1 BUCK5_VSET1 0xb2 1.80 V BUCK5_VOUT_2 BUCK5_VSET2 0xb2 1.80 V BUCK1_PG_WINDOW BUCK1_OV_THR 0x3 +5% / +50 mV BUCK1_UV_THR 0x3 -5% / -50 mV BUCK2_PG_WINDOW BUCK2_OV_THR 0x3 +5% / +50 mV BUCK2_UV_THR 0x3 -5% / -50 mV BUCK3_PG_WINDOW BUCK3_OV_THR 0x3 +5% / +50 mV BUCK3_UV_THR 0x3 -5% / -50 mV BUCK4_PG_WINDOW BUCK4_OV_THR 0x4 +6% / +60 mV BUCK4_UV_THR 0x4 -6% / -60 mV BUCK5_PG_WINDOW BUCK5_OV_THR 0x4 +6% / +60 mV BUCK5_UV_THR 0x4 -6% / -60 mV BUCK NVM Settings Register Name Field Name TPS65931211-Q1 Value Description BUCK1_CTRL BUCK1_EN 0x0 Disabled; BUCK1 regulator BUCK1_FPWM 0x1 PWM operation only. BUCK1_FPWM_MP 0x0 Automatic phase adding and shedding. BUCK1_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK1_VSEL 0x0 BUCK1_VOUT_1 BUCK1_PLDN 0x1 Enabled; Pull-down resistor BUCK1_RV_SEL 0x0 Disabled BUCK1_CONF BUCK1_SLEW_RATE 0x3 5.0 mV/μs BUCK1_ILIM 0x5 5.5 A BUCK2_CTRL BUCK2_EN 0x0 Disabled; BUCK2 regulator BUCK2_FPWM 0x1 PWM operation only. BUCK2_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK2_VSEL 0x0 BUCK2_VOUT_1 BUCK2_PLDN 0x1 Enabled; Pull-down resistor BUCK2_RV_SEL 0x0 Disabled BUCK2_CONF BUCK2_SLEW_RATE 0x3 5.0 mV/μs BUCK2_ILIM 0x5 5.5 A BUCK3_CTRL BUCK3_EN 0x0 Disabled; BUCK3 regulator BUCK3_FPWM 0x1 PWM operation only. BUCK3_FPWM_MP 0x0 Automatic phase adding and shedding. BUCK3_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK3_VSEL 0x0 BUCK3_VOUT_1 BUCK3_PLDN 0x1 Enabled; Pull-down resistor BUCK3_RV_SEL 0x0 Disabled BUCK3_CONF BUCK3_SLEW_RATE 0x0 33 mV/μs BUCK3_ILIM 0x5 5.5 A BUCK4_CTRL BUCK4_EN 0x0 Disabled; BUCK4 regulator BUCK4_FPWM 0x0 PFM and PWM operation (AUTO mode). BUCK4_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK4_VSEL 0x0 BUCK4_VOUT_1 BUCK4_PLDN 0x1 Enabled; Pull-down resistor BUCK4_RV_SEL 0x0 Disabled BUCK4_CONF BUCK4_SLEW_RATE 0x3 5.0 mV/μs BUCK4_ILIM 0x5 5.5 A BUCK5_CTRL BUCK5_EN 0x0 Disabled; BUCK5 regulator BUCK5_FPWM 0x0 PFM and PWM operation (AUTO mode). BUCK5_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK5_VSEL 0x0 BUCK5_VOUT_1 BUCK5_PLDN 0x1 Enable Pull-down resistor BUCK5_RV_SEL 0x0 Disabled BUCK5_CONF BUCK5_SLEW_RATE 0x3 5.0 mV/μs BUCK5_ILIM 0x3 3.5 A BUCK1_VOUT_1 BUCK1_VSET1 0x2d 0.750 V BUCK1_VOUT_2 BUCK1_VSET2 0x2d 0.750 V BUCK2_VOUT_1 BUCK2_VSET1 0x2d 0.750 V BUCK2_VOUT_2 BUCK2_VSET2 0x2d 0.750 V BUCK3_VOUT_1 BUCK3_VSET1 0xfd 3.30 V BUCK3_VOUT_2 BUCK3_VSET2 0xfd 3.30 V BUCK4_VOUT_1 BUCK4_VSET1 0x73 1.10 V BUCK4_VOUT_2 BUCK4_VSET2 0x73 1.10 V BUCK5_VOUT_1 BUCK5_VSET1 0xb2 1.80 V BUCK5_VOUT_2 BUCK5_VSET2 0xb2 1.80 V BUCK1_PG_WINDOW BUCK1_OV_THR 0x3 +5% / +50 mV BUCK1_UV_THR 0x3 -5% / -50 mV BUCK2_PG_WINDOW BUCK2_OV_THR 0x3 +5% / +50 mV BUCK2_UV_THR 0x3 -5% / -50 mV BUCK3_PG_WINDOW BUCK3_OV_THR 0x3 +5% / +50 mV BUCK3_UV_THR 0x3 -5% / -50 mV BUCK4_PG_WINDOW BUCK4_OV_THR 0x4 +6% / +60 mV BUCK4_UV_THR 0x4 -6% / -60 mV BUCK5_PG_WINDOW BUCK5_OV_THR 0x4 +6% / +60 mV BUCK5_UV_THR 0x4 -6% / -60 mV Register Name Field Name TPS65931211-Q1 Value Description Register Name Field Name TPS65931211-Q1 Register NameField Name TPS65931211-Q1 TPS65931211-Q1 Value Description ValueDescription BUCK1_CTRL BUCK1_EN 0x0 Disabled; BUCK1 regulator BUCK1_FPWM 0x1 PWM operation only. BUCK1_FPWM_MP 0x0 Automatic phase adding and shedding. BUCK1_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK1_VSEL 0x0 BUCK1_VOUT_1 BUCK1_PLDN 0x1 Enabled; Pull-down resistor BUCK1_RV_SEL 0x0 Disabled BUCK1_CONF BUCK1_SLEW_RATE 0x3 5.0 mV/μs BUCK1_ILIM 0x5 5.5 A BUCK2_CTRL BUCK2_EN 0x0 Disabled; BUCK2 regulator BUCK2_FPWM 0x1 PWM operation only. BUCK2_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK2_VSEL 0x0 BUCK2_VOUT_1 BUCK2_PLDN 0x1 Enabled; Pull-down resistor BUCK2_RV_SEL 0x0 Disabled BUCK2_CONF BUCK2_SLEW_RATE 0x3 5.0 mV/μs BUCK2_ILIM 0x5 5.5 A BUCK3_CTRL BUCK3_EN 0x0 Disabled; BUCK3 regulator BUCK3_FPWM 0x1 PWM operation only. BUCK3_FPWM_MP 0x0 Automatic phase adding and shedding. BUCK3_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK3_VSEL 0x0 BUCK3_VOUT_1 BUCK3_PLDN 0x1 Enabled; Pull-down resistor BUCK3_RV_SEL 0x0 Disabled BUCK3_CONF BUCK3_SLEW_RATE 0x0 33 mV/μs BUCK3_ILIM 0x5 5.5 A BUCK4_CTRL BUCK4_EN 0x0 Disabled; BUCK4 regulator BUCK4_FPWM 0x0 PFM and PWM operation (AUTO mode). BUCK4_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK4_VSEL 0x0 BUCK4_VOUT_1 BUCK4_PLDN 0x1 Enabled; Pull-down resistor BUCK4_RV_SEL 0x0 Disabled BUCK4_CONF BUCK4_SLEW_RATE 0x3 5.0 mV/μs BUCK4_ILIM 0x5 5.5 A BUCK5_CTRL BUCK5_EN 0x0 Disabled; BUCK5 regulator BUCK5_FPWM 0x0 PFM and PWM operation (AUTO mode). BUCK5_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK5_VSEL 0x0 BUCK5_VOUT_1 BUCK5_PLDN 0x1 Enable Pull-down resistor BUCK5_RV_SEL 0x0 Disabled BUCK5_CONF BUCK5_SLEW_RATE 0x3 5.0 mV/μs BUCK5_ILIM 0x3 3.5 A BUCK1_VOUT_1 BUCK1_VSET1 0x2d 0.750 V BUCK1_VOUT_2 BUCK1_VSET2 0x2d 0.750 V BUCK2_VOUT_1 BUCK2_VSET1 0x2d 0.750 V BUCK2_VOUT_2 BUCK2_VSET2 0x2d 0.750 V BUCK3_VOUT_1 BUCK3_VSET1 0xfd 3.30 V BUCK3_VOUT_2 BUCK3_VSET2 0xfd 3.30 V BUCK4_VOUT_1 BUCK4_VSET1 0x73 1.10 V BUCK4_VOUT_2 BUCK4_VSET2 0x73 1.10 V BUCK5_VOUT_1 BUCK5_VSET1 0xb2 1.80 V BUCK5_VOUT_2 BUCK5_VSET2 0xb2 1.80 V BUCK1_PG_WINDOW BUCK1_OV_THR 0x3 +5% / +50 mV BUCK1_UV_THR 0x3 -5% / -50 mV BUCK2_PG_WINDOW BUCK2_OV_THR 0x3 +5% / +50 mV BUCK2_UV_THR 0x3 -5% / -50 mV BUCK3_PG_WINDOW BUCK3_OV_THR 0x3 +5% / +50 mV BUCK3_UV_THR 0x3 -5% / -50 mV BUCK4_PG_WINDOW BUCK4_OV_THR 0x4 +6% / +60 mV BUCK4_UV_THR 0x4 -6% / -60 mV BUCK5_PG_WINDOW BUCK5_OV_THR 0x4 +6% / +60 mV BUCK5_UV_THR 0x4 -6% / -60 mV BUCK1_CTRL BUCK1_EN 0x0 Disabled; BUCK1 regulator BUCK1_CTRLBUCK1_EN 0x0 0x0 Disabled; BUCK1 regulator Disabled; BUCK1 regulator BUCK1_FPWM 0x1 PWM operation only. BUCK1_FPWM 0x1 0x1 PWM operation only. PWM operation only. BUCK1_FPWM_MP 0x0 Automatic phase adding and shedding. BUCK1_FPWM_MP 0x0 0x0 Automatic phase adding and shedding. Automatic phase adding and shedding. BUCK1_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK1_VMON_EN 0x0 0x0 Disabled; OV, UV, SC and ILIM comparators. Disabled; OV, UV, SC and ILIM comparators. BUCK1_VSEL 0x0 BUCK1_VOUT_1 BUCK1_VSEL 0x0 0x0 BUCK1_VOUT_1 BUCK1_VOUT_1 BUCK1_PLDN 0x1 Enabled; Pull-down resistor BUCK1_PLDN 0x1 0x1 Enabled; Pull-down resistor Enabled; Pull-down resistor BUCK1_RV_SEL 0x0 Disabled BUCK1_RV_SEL 0x0 0x0 Disabled Disabled BUCK1_CONF BUCK1_SLEW_RATE 0x3 5.0 mV/μs BUCK1_CONFBUCK1_SLEW_RATE 0x3 0x3 5.0 mV/μs 5.0 mV/μs BUCK1_ILIM 0x5 5.5 A BUCK1_ILIM 0x5 0x5 5.5 A 5.5 A BUCK2_CTRL BUCK2_EN 0x0 Disabled; BUCK2 regulator BUCK2_CTRLBUCK2_EN 0x0 0x0 Disabled; BUCK2 regulator Disabled; BUCK2 regulator BUCK2_FPWM 0x1 PWM operation only. BUCK2_FPWM 0x1 0x1 PWM operation only. PWM operation only. BUCK2_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK2_VMON_EN 0x0 0x0 Disabled; OV, UV, SC and ILIM comparators. Disabled; OV, UV, SC and ILIM comparators. BUCK2_VSEL 0x0 BUCK2_VOUT_1 BUCK2_VSEL 0x0 0x0 BUCK2_VOUT_1 BUCK2_VOUT_1 BUCK2_PLDN 0x1 Enabled; Pull-down resistor BUCK2_PLDN 0x1 0x1 Enabled; Pull-down resistor Enabled; Pull-down resistor BUCK2_RV_SEL 0x0 Disabled BUCK2_RV_SEL 0x0 0x0 Disabled Disabled BUCK2_CONF BUCK2_SLEW_RATE 0x3 5.0 mV/μs BUCK2_CONFBUCK2_SLEW_RATE 0x3 0x3 5.0 mV/μs 5.0 mV/μs BUCK2_ILIM 0x5 5.5 A BUCK2_ILIM 0x5 0x5 5.5 A 5.5 A BUCK3_CTRL BUCK3_EN 0x0 Disabled; BUCK3 regulator BUCK3_CTRLBUCK3_EN 0x0 0x0 Disabled; BUCK3 regulator Disabled; BUCK3 regulator BUCK3_FPWM 0x1 PWM operation only. BUCK3_FPWM 0x1 0x1 PWM operation only. PWM operation only. BUCK3_FPWM_MP 0x0 Automatic phase adding and shedding. BUCK3_FPWM_MP 0x0 0x0 Automatic phase adding and shedding. Automatic phase adding and shedding. BUCK3_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK3_VMON_EN 0x0 0x0 Disabled; OV, UV, SC and ILIM comparators. Disabled; OV, UV, SC and ILIM comparators. BUCK3_VSEL 0x0 BUCK3_VOUT_1 BUCK3_VSEL 0x0 0x0 BUCK3_VOUT_1 BUCK3_VOUT_1 BUCK3_PLDN 0x1 Enabled; Pull-down resistor BUCK3_PLDN 0x1 0x1 Enabled; Pull-down resistor Enabled; Pull-down resistor BUCK3_RV_SEL 0x0 Disabled BUCK3_RV_SEL 0x0 0x0 Disabled Disabled BUCK3_CONF BUCK3_SLEW_RATE 0x0 33 mV/μs BUCK3_CONFBUCK3_SLEW_RATE 0x0 0x0 33 mV/μs 33 mV/μs BUCK3_ILIM 0x5 5.5 A BUCK3_ILIM 0x5 0x5 5.5 A 5.5 A BUCK4_CTRL BUCK4_EN 0x0 Disabled; BUCK4 regulator BUCK4_CTRLBUCK4_EN 0x0 0x0 Disabled; BUCK4 regulator Disabled; BUCK4 regulator BUCK4_FPWM 0x0 PFM and PWM operation (AUTO mode). BUCK4_FPWM 0x0 0x0 PFM and PWM operation (AUTO mode). PFM and PWM operation (AUTO mode). BUCK4_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK4_VMON_EN 0x0 0x0 Disabled; OV, UV, SC and ILIM comparators. Disabled; OV, UV, SC and ILIM comparators. BUCK4_VSEL 0x0 BUCK4_VOUT_1 BUCK4_VSEL 0x0 0x0 BUCK4_VOUT_1 BUCK4_VOUT_1 BUCK4_PLDN 0x1 Enabled; Pull-down resistor BUCK4_PLDN 0x1 0x1 Enabled; Pull-down resistor Enabled; Pull-down resistor BUCK4_RV_SEL 0x0 Disabled BUCK4_RV_SEL 0x0 0x0 Disabled Disabled BUCK4_CONF BUCK4_SLEW_RATE 0x3 5.0 mV/μs BUCK4_CONFBUCK4_SLEW_RATE 0x3 0x3 5.0 mV/μs 5.0 mV/μs BUCK4_ILIM 0x5 5.5 A BUCK4_ILIM 0x5 0x5 5.5 A 5.5 A BUCK5_CTRL BUCK5_EN 0x0 Disabled; BUCK5 regulator BUCK5_CTRLBUCK5_EN 0x0 0x0 Disabled; BUCK5 regulator Disabled; BUCK5 regulator BUCK5_FPWM 0x0 PFM and PWM operation (AUTO mode). BUCK5_FPWM 0x0 0x0 PFM and PWM operation (AUTO mode). PFM and PWM operation (AUTO mode). BUCK5_VMON_EN 0x0 Disabled; OV, UV, SC and ILIM comparators. BUCK5_VMON_EN 0x0 0x0 Disabled; OV, UV, SC and ILIM comparators. Disabled; OV, UV, SC and ILIM comparators. BUCK5_VSEL 0x0 BUCK5_VOUT_1 BUCK5_VSEL 0x0 0x0 BUCK5_VOUT_1 BUCK5_VOUT_1 BUCK5_PLDN 0x1 Enable Pull-down resistor BUCK5_PLDN 0x1 0x1 Enable Pull-down resistor Enable Pull-down resistor BUCK5_RV_SEL 0x0 Disabled BUCK5_RV_SEL 0x0 0x0 Disabled Disabled BUCK5_CONF BUCK5_SLEW_RATE 0x3 5.0 mV/μs BUCK5_CONFBUCK5_SLEW_RATE 0x3 0x3 5.0 mV/μs 5.0 mV/μs BUCK5_ILIM 0x3 3.5 A BUCK5_ILIM 0x3 0x3 3.5 A 3.5 A BUCK1_VOUT_1 BUCK1_VSET1 0x2d 0.750 V BUCK1_VOUT_1BUCK1_VSET1 0x2d 0x2d 0.750 V 0.750 V BUCK1_VOUT_2 BUCK1_VSET2 0x2d 0.750 V BUCK1_VOUT_2BUCK1_VSET2 0x2d 0x2d 0.750 V 0.750 V BUCK2_VOUT_1 BUCK2_VSET1 0x2d 0.750 V BUCK2_VOUT_1BUCK2_VSET1 0x2d 0x2d 0.750 V 0.750 V BUCK2_VOUT_2 BUCK2_VSET2 0x2d 0.750 V BUCK2_VOUT_2BUCK2_VSET2 0x2d 0x2d 0.750 V 0.750 V BUCK3_VOUT_1 BUCK3_VSET1 0xfd 3.30 V BUCK3_VOUT_1BUCK3_VSET1 0xfd 0xfd 3.30 V 3.30 V BUCK3_VOUT_2 BUCK3_VSET2 0xfd 3.30 V BUCK3_VOUT_2BUCK3_VSET2 0xfd 0xfd 3.30 V 3.30 V BUCK4_VOUT_1 BUCK4_VSET1 0x73 1.10 V BUCK4_VOUT_1BUCK4_VSET1 0x73 0x73 1.10 V 1.10 V BUCK4_VOUT_2 BUCK4_VSET2 0x73 1.10 V BUCK4_VOUT_2BUCK4_VSET2 0x73 0x73 1.10 V 1.10 V BUCK5_VOUT_1 BUCK5_VSET1 0xb2 1.80 V BUCK5_VOUT_1BUCK5_VSET1 0xb2 0xb2 1.80 V 1.80 V BUCK5_VOUT_2 BUCK5_VSET2 0xb2 1.80 V BUCK5_VOUT_2BUCK5_VSET2 0xb2 0xb2 1.80 V 1.80 V BUCK1_PG_WINDOW BUCK1_OV_THR 0x3 +5% / +50 mV BUCK1_PG_WINDOWBUCK1_OV_THR 0x3 0x3 +5% / +50 mV +5% / +50 mV BUCK1_UV_THR 0x3 -5% / -50 mV BUCK1_UV_THR 0x3 0x3 -5% / -50 mV -5% / -50 mV BUCK2_PG_WINDOW BUCK2_OV_THR 0x3 +5% / +50 mV BUCK2_PG_WINDOWBUCK2_OV_THR 0x3 0x3 +5% / +50 mV +5% / +50 mV BUCK2_UV_THR 0x3 -5% / -50 mV BUCK2_UV_THR 0x3 0x3 -5% / -50 mV -5% / -50 mV BUCK3_PG_WINDOW BUCK3_OV_THR 0x3 +5% / +50 mV BUCK3_PG_WINDOWBUCK3_OV_THR 0x3 0x3 +5% / +50 mV +5% / +50 mV BUCK3_UV_THR 0x3 -5% / -50 mV BUCK3_UV_THR 0x3 0x3 -5% / -50 mV -5% / -50 mV BUCK4_PG_WINDOW BUCK4_OV_THR 0x4 +6% / +60 mV BUCK4_PG_WINDOWBUCK4_OV_THR 0x4 0x4 +6% / +60 mV +6% / +60 mV BUCK4_UV_THR 0x4 -6% / -60 mV BUCK4_UV_THR 0x4 0x4 -6% / -60 mV -6% / -60 mV BUCK5_PG_WINDOW BUCK5_OV_THR 0x4 +6% / +60 mV BUCK5_PG_WINDOWBUCK5_OV_THR 0x4 0x4 +6% / +60 mV +6% / +60 mV BUCK5_UV_THR 0x4 -6% / -60 mV BUCK5_UV_THR 0x4 0x4 -6% / -60 mV -6% / -60 mV LDO Settings These settings detail the voltages, configurations, and monitoring of the LDO rails stored in the NVM. All these settings can be changed though I2C after startup. Some settings, typically the enable bits, are also changed by the PFSM, as described in . After the sequence has completed, the LDOx_EN and LDOx_VMON_EN bits are set and the LDOx_RV_SEL bit is cleared for all LDOs. The other bits remain unchanged, but are still accessible via I2C. LDO NVM Settings Register Name Field Name TPS65931211-Q1 Value Description LDO1_CTRL LDO1_EN 0x0 Disabled; LDO1 regulator. LDO1_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO1_PLDN 0x1 125 Ohm LDO1_VMON_EN 0x0 Disable OV and UV comparators. LDO1_RV_SEL 0x0 Disabled LDO2_CTRL LDO2_EN 0x0 Disabled; LDO2 regulator. LDO2_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO2_PLDN 0x0 50 kOhm LDO2_VMON_EN 0x0 Disabled; OV and UV comparators. LDO2_RV_SEL 0x0 Disabled LDO3_CTRL LDO3_EN 0x0 Disabled; LDO3 regulator. LDO3_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO3_PLDN 0x1 125 Ohm LDO3_VMON_EN 0x0 Disabled; OV and UV comparators. LDO3_RV_SEL 0x0 Disabled LDO4_CTRL LDO4_EN 0x0 Disabled; LDO4 regulator. LDO4_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO4_PLDN 0x1 125 Ohm LDO4_VMON_EN 0x0 Disabled; OV and UV comparators. LDO4_RV_SEL 0x0 Disabled LDO1_VOUT LDO1_VSET 0x3a 3.30 V LDO1_BYPASS 0x1 Bypass mode. LDO2_VOUT LDO2_VSET 0x1c 1.80 V LDO2_BYPASS 0x0 Linear regulator mode. LDO3_VOUT LDO3_VSET 0x9 0.85 V LDO3_BYPASS 0x0 Linear regulator mode. LDO4_VOUT LDO4_VSET 0x38 1.800 V LDO1_PG_WINDOW LDO1_OV_THR 0x4 +6% / +60 mV LDO1_UV_THR 0x4 -6% / -60 mV LDO2_PG_WINDOW LDO2_OV_THR 0x4 +6% / +60 mV LDO2_UV_THR 0x4 -6% / -60 mV LDO3_PG_WINDOW LDO3_OV_THR 0x4 +6% / +60 mV LDO3_UV_THR 0x4 -6% / -60 mV LDO4_PG_WINDOW LDO4_OV_THR 0x4 +6% / +60 mV LDO4_UV_THR 0x4 -6% / -60 mV LDO Settings These settings detail the voltages, configurations, and monitoring of the LDO rails stored in the NVM. All these settings can be changed though I2C after startup. Some settings, typically the enable bits, are also changed by the PFSM, as described in . After the sequence has completed, the LDOx_EN and LDOx_VMON_EN bits are set and the LDOx_RV_SEL bit is cleared for all LDOs. The other bits remain unchanged, but are still accessible via I2C. LDO NVM Settings Register Name Field Name TPS65931211-Q1 Value Description LDO1_CTRL LDO1_EN 0x0 Disabled; LDO1 regulator. LDO1_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO1_PLDN 0x1 125 Ohm LDO1_VMON_EN 0x0 Disable OV and UV comparators. LDO1_RV_SEL 0x0 Disabled LDO2_CTRL LDO2_EN 0x0 Disabled; LDO2 regulator. LDO2_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO2_PLDN 0x0 50 kOhm LDO2_VMON_EN 0x0 Disabled; OV and UV comparators. LDO2_RV_SEL 0x0 Disabled LDO3_CTRL LDO3_EN 0x0 Disabled; LDO3 regulator. LDO3_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO3_PLDN 0x1 125 Ohm LDO3_VMON_EN 0x0 Disabled; OV and UV comparators. LDO3_RV_SEL 0x0 Disabled LDO4_CTRL LDO4_EN 0x0 Disabled; LDO4 regulator. LDO4_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO4_PLDN 0x1 125 Ohm LDO4_VMON_EN 0x0 Disabled; OV and UV comparators. LDO4_RV_SEL 0x0 Disabled LDO1_VOUT LDO1_VSET 0x3a 3.30 V LDO1_BYPASS 0x1 Bypass mode. LDO2_VOUT LDO2_VSET 0x1c 1.80 V LDO2_BYPASS 0x0 Linear regulator mode. LDO3_VOUT LDO3_VSET 0x9 0.85 V LDO3_BYPASS 0x0 Linear regulator mode. LDO4_VOUT LDO4_VSET 0x38 1.800 V LDO1_PG_WINDOW LDO1_OV_THR 0x4 +6% / +60 mV LDO1_UV_THR 0x4 -6% / -60 mV LDO2_PG_WINDOW LDO2_OV_THR 0x4 +6% / +60 mV LDO2_UV_THR 0x4 -6% / -60 mV LDO3_PG_WINDOW LDO3_OV_THR 0x4 +6% / +60 mV LDO3_UV_THR 0x4 -6% / -60 mV LDO4_PG_WINDOW LDO4_OV_THR 0x4 +6% / +60 mV LDO4_UV_THR 0x4 -6% / -60 mV These settings detail the voltages, configurations, and monitoring of the LDO rails stored in the NVM. All these settings can be changed though I2C after startup. Some settings, typically the enable bits, are also changed by the PFSM, as described in . After the sequence has completed, the LDOx_EN and LDOx_VMON_EN bits are set and the LDOx_RV_SEL bit is cleared for all LDOs. The other bits remain unchanged, but are still accessible via I2C. LDO NVM Settings Register Name Field Name TPS65931211-Q1 Value Description LDO1_CTRL LDO1_EN 0x0 Disabled; LDO1 regulator. LDO1_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO1_PLDN 0x1 125 Ohm LDO1_VMON_EN 0x0 Disable OV and UV comparators. LDO1_RV_SEL 0x0 Disabled LDO2_CTRL LDO2_EN 0x0 Disabled; LDO2 regulator. LDO2_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO2_PLDN 0x0 50 kOhm LDO2_VMON_EN 0x0 Disabled; OV and UV comparators. LDO2_RV_SEL 0x0 Disabled LDO3_CTRL LDO3_EN 0x0 Disabled; LDO3 regulator. LDO3_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO3_PLDN 0x1 125 Ohm LDO3_VMON_EN 0x0 Disabled; OV and UV comparators. LDO3_RV_SEL 0x0 Disabled LDO4_CTRL LDO4_EN 0x0 Disabled; LDO4 regulator. LDO4_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO4_PLDN 0x1 125 Ohm LDO4_VMON_EN 0x0 Disabled; OV and UV comparators. LDO4_RV_SEL 0x0 Disabled LDO1_VOUT LDO1_VSET 0x3a 3.30 V LDO1_BYPASS 0x1 Bypass mode. LDO2_VOUT LDO2_VSET 0x1c 1.80 V LDO2_BYPASS 0x0 Linear regulator mode. LDO3_VOUT LDO3_VSET 0x9 0.85 V LDO3_BYPASS 0x0 Linear regulator mode. LDO4_VOUT LDO4_VSET 0x38 1.800 V LDO1_PG_WINDOW LDO1_OV_THR 0x4 +6% / +60 mV LDO1_UV_THR 0x4 -6% / -60 mV LDO2_PG_WINDOW LDO2_OV_THR 0x4 +6% / +60 mV LDO2_UV_THR 0x4 -6% / -60 mV LDO3_PG_WINDOW LDO3_OV_THR 0x4 +6% / +60 mV LDO3_UV_THR 0x4 -6% / -60 mV LDO4_PG_WINDOW LDO4_OV_THR 0x4 +6% / +60 mV LDO4_UV_THR 0x4 -6% / -60 mV These settings detail the voltages, configurations, and monitoring of the LDO rails stored in the NVM. All these settings can be changed though I2C after startup. Some settings, typically the enable bits, are also changed by the PFSM, as described in .2After the sequence has completed, the LDOx_EN and LDOx_VMON_EN bits are set and the LDOx_RV_SEL bit is cleared for all LDOs. The other bits remain unchanged, but are still accessible via I2C.2 LDO NVM Settings Register Name Field Name TPS65931211-Q1 Value Description LDO1_CTRL LDO1_EN 0x0 Disabled; LDO1 regulator. LDO1_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO1_PLDN 0x1 125 Ohm LDO1_VMON_EN 0x0 Disable OV and UV comparators. LDO1_RV_SEL 0x0 Disabled LDO2_CTRL LDO2_EN 0x0 Disabled; LDO2 regulator. LDO2_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO2_PLDN 0x0 50 kOhm LDO2_VMON_EN 0x0 Disabled; OV and UV comparators. LDO2_RV_SEL 0x0 Disabled LDO3_CTRL LDO3_EN 0x0 Disabled; LDO3 regulator. LDO3_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO3_PLDN 0x1 125 Ohm LDO3_VMON_EN 0x0 Disabled; OV and UV comparators. LDO3_RV_SEL 0x0 Disabled LDO4_CTRL LDO4_EN 0x0 Disabled; LDO4 regulator. LDO4_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO4_PLDN 0x1 125 Ohm LDO4_VMON_EN 0x0 Disabled; OV and UV comparators. LDO4_RV_SEL 0x0 Disabled LDO1_VOUT LDO1_VSET 0x3a 3.30 V LDO1_BYPASS 0x1 Bypass mode. LDO2_VOUT LDO2_VSET 0x1c 1.80 V LDO2_BYPASS 0x0 Linear regulator mode. LDO3_VOUT LDO3_VSET 0x9 0.85 V LDO3_BYPASS 0x0 Linear regulator mode. LDO4_VOUT LDO4_VSET 0x38 1.800 V LDO1_PG_WINDOW LDO1_OV_THR 0x4 +6% / +60 mV LDO1_UV_THR 0x4 -6% / -60 mV LDO2_PG_WINDOW LDO2_OV_THR 0x4 +6% / +60 mV LDO2_UV_THR 0x4 -6% / -60 mV LDO3_PG_WINDOW LDO3_OV_THR 0x4 +6% / +60 mV LDO3_UV_THR 0x4 -6% / -60 mV LDO4_PG_WINDOW LDO4_OV_THR 0x4 +6% / +60 mV LDO4_UV_THR 0x4 -6% / -60 mV LDO NVM Settings Register Name Field Name TPS65931211-Q1 Value Description LDO1_CTRL LDO1_EN 0x0 Disabled; LDO1 regulator. LDO1_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO1_PLDN 0x1 125 Ohm LDO1_VMON_EN 0x0 Disable OV and UV comparators. LDO1_RV_SEL 0x0 Disabled LDO2_CTRL LDO2_EN 0x0 Disabled; LDO2 regulator. LDO2_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO2_PLDN 0x0 50 kOhm LDO2_VMON_EN 0x0 Disabled; OV and UV comparators. LDO2_RV_SEL 0x0 Disabled LDO3_CTRL LDO3_EN 0x0 Disabled; LDO3 regulator. LDO3_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO3_PLDN 0x1 125 Ohm LDO3_VMON_EN 0x0 Disabled; OV and UV comparators. LDO3_RV_SEL 0x0 Disabled LDO4_CTRL LDO4_EN 0x0 Disabled; LDO4 regulator. LDO4_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO4_PLDN 0x1 125 Ohm LDO4_VMON_EN 0x0 Disabled; OV and UV comparators. LDO4_RV_SEL 0x0 Disabled LDO1_VOUT LDO1_VSET 0x3a 3.30 V LDO1_BYPASS 0x1 Bypass mode. LDO2_VOUT LDO2_VSET 0x1c 1.80 V LDO2_BYPASS 0x0 Linear regulator mode. LDO3_VOUT LDO3_VSET 0x9 0.85 V LDO3_BYPASS 0x0 Linear regulator mode. LDO4_VOUT LDO4_VSET 0x38 1.800 V LDO1_PG_WINDOW LDO1_OV_THR 0x4 +6% / +60 mV LDO1_UV_THR 0x4 -6% / -60 mV LDO2_PG_WINDOW LDO2_OV_THR 0x4 +6% / +60 mV LDO2_UV_THR 0x4 -6% / -60 mV LDO3_PG_WINDOW LDO3_OV_THR 0x4 +6% / +60 mV LDO3_UV_THR 0x4 -6% / -60 mV LDO4_PG_WINDOW LDO4_OV_THR 0x4 +6% / +60 mV LDO4_UV_THR 0x4 -6% / -60 mV Register Name Field Name TPS65931211-Q1 Value Description Register Name Field Name TPS65931211-Q1 Register NameField Name TPS65931211-Q1 TPS65931211-Q1 Value Description ValueDescription LDO1_CTRL LDO1_EN 0x0 Disabled; LDO1 regulator. LDO1_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO1_PLDN 0x1 125 Ohm LDO1_VMON_EN 0x0 Disable OV and UV comparators. LDO1_RV_SEL 0x0 Disabled LDO2_CTRL LDO2_EN 0x0 Disabled; LDO2 regulator. LDO2_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO2_PLDN 0x0 50 kOhm LDO2_VMON_EN 0x0 Disabled; OV and UV comparators. LDO2_RV_SEL 0x0 Disabled LDO3_CTRL LDO3_EN 0x0 Disabled; LDO3 regulator. LDO3_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO3_PLDN 0x1 125 Ohm LDO3_VMON_EN 0x0 Disabled; OV and UV comparators. LDO3_RV_SEL 0x0 Disabled LDO4_CTRL LDO4_EN 0x0 Disabled; LDO4 regulator. LDO4_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO4_PLDN 0x1 125 Ohm LDO4_VMON_EN 0x0 Disabled; OV and UV comparators. LDO4_RV_SEL 0x0 Disabled LDO1_VOUT LDO1_VSET 0x3a 3.30 V LDO1_BYPASS 0x1 Bypass mode. LDO2_VOUT LDO2_VSET 0x1c 1.80 V LDO2_BYPASS 0x0 Linear regulator mode. LDO3_VOUT LDO3_VSET 0x9 0.85 V LDO3_BYPASS 0x0 Linear regulator mode. LDO4_VOUT LDO4_VSET 0x38 1.800 V LDO1_PG_WINDOW LDO1_OV_THR 0x4 +6% / +60 mV LDO1_UV_THR 0x4 -6% / -60 mV LDO2_PG_WINDOW LDO2_OV_THR 0x4 +6% / +60 mV LDO2_UV_THR 0x4 -6% / -60 mV LDO3_PG_WINDOW LDO3_OV_THR 0x4 +6% / +60 mV LDO3_UV_THR 0x4 -6% / -60 mV LDO4_PG_WINDOW LDO4_OV_THR 0x4 +6% / +60 mV LDO4_UV_THR 0x4 -6% / -60 mV LDO1_CTRL LDO1_EN 0x0 Disabled; LDO1 regulator. LDO1_CTRLLDO1_EN 0x0 0x0 Disabled; LDO1 regulator. Disabled; LDO1 regulator. LDO1_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO1_SLOW_RAMP 0x1 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO1_PLDN 0x1 125 Ohm LDO1_PLDN 0x1 0x1 125 Ohm 125 Ohm LDO1_VMON_EN 0x0 Disable OV and UV comparators. LDO1_VMON_EN 0x0 0x0 Disable OV and UV comparators. Disable OV and UV comparators. LDO1_RV_SEL 0x0 Disabled LDO1_RV_SEL 0x0 0x0 Disabled Disabled LDO2_CTRL LDO2_EN 0x0 Disabled; LDO2 regulator. LDO2_CTRLLDO2_EN 0x0 0x0 Disabled; LDO2 regulator. Disabled; LDO2 regulator. LDO2_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO2_SLOW_RAMP 0x1 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO2_PLDN 0x0 50 kOhm LDO2_PLDN 0x0 0x0 50 kOhm 50 kOhm LDO2_VMON_EN 0x0 Disabled; OV and UV comparators. LDO2_VMON_EN 0x0 0x0 Disabled; OV and UV comparators. Disabled; OV and UV comparators. LDO2_RV_SEL 0x0 Disabled LDO2_RV_SEL 0x0 0x0 Disabled Disabled LDO3_CTRL LDO3_EN 0x0 Disabled; LDO3 regulator. LDO3_CTRLLDO3_EN 0x0 0x0 Disabled; LDO3 regulator. Disabled; LDO3 regulator. LDO3_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO3_SLOW_RAMP 0x1 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO3_PLDN 0x1 125 Ohm LDO3_PLDN 0x1 0x1 125 Ohm 125 Ohm LDO3_VMON_EN 0x0 Disabled; OV and UV comparators. LDO3_VMON_EN 0x0 0x0 Disabled; OV and UV comparators. Disabled; OV and UV comparators. LDO3_RV_SEL 0x0 Disabled LDO3_RV_SEL 0x0 0x0 Disabled Disabled LDO4_CTRL LDO4_EN 0x0 Disabled; LDO4 regulator. LDO4_CTRLLDO4_EN 0x0 0x0 Disabled; LDO4 regulator. Disabled; LDO4 regulator. LDO4_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO4_SLOW_RAMP 0x1 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET LDO4_PLDN 0x1 125 Ohm LDO4_PLDN 0x1 0x1 125 Ohm 125 Ohm LDO4_VMON_EN 0x0 Disabled; OV and UV comparators. LDO4_VMON_EN 0x0 0x0 Disabled; OV and UV comparators. Disabled; OV and UV comparators. LDO4_RV_SEL 0x0 Disabled LDO4_RV_SEL 0x0 0x0 Disabled Disabled LDO1_VOUT LDO1_VSET 0x3a 3.30 V LDO1_VOUTLDO1_VSET 0x3a 0x3a 3.30 V 3.30 V LDO1_BYPASS 0x1 Bypass mode. LDO1_BYPASS 0x1 0x1 Bypass mode. Bypass mode. LDO2_VOUT LDO2_VSET 0x1c 1.80 V LDO2_VOUTLDO2_VSET 0x1c 0x1c 1.80 V 1.80 V LDO2_BYPASS 0x0 Linear regulator mode. LDO2_BYPASS 0x0 0x0 Linear regulator mode. Linear regulator mode. LDO3_VOUT LDO3_VSET 0x9 0.85 V LDO3_VOUTLDO3_VSET 0x9 0x9 0.85 V 0.85 V LDO3_BYPASS 0x0 Linear regulator mode. LDO3_BYPASS 0x0 0x0 Linear regulator mode. Linear regulator mode. LDO4_VOUT LDO4_VSET 0x38 1.800 V LDO4_VOUTLDO4_VSET 0x38 0x38 1.800 V 1.800 V LDO1_PG_WINDOW LDO1_OV_THR 0x4 +6% / +60 mV LDO1_PG_WINDOWLDO1_OV_THR 0x4 0x4 +6% / +60 mV +6% / +60 mV LDO1_UV_THR 0x4 -6% / -60 mV LDO1_UV_THR 0x4 0x4 -6% / -60 mV -6% / -60 mV LDO2_PG_WINDOW LDO2_OV_THR 0x4 +6% / +60 mV LDO2_PG_WINDOWLDO2_OV_THR 0x4 0x4 +6% / +60 mV +6% / +60 mV LDO2_UV_THR 0x4 -6% / -60 mV LDO2_UV_THR 0x4 0x4 -6% / -60 mV -6% / -60 mV LDO3_PG_WINDOW LDO3_OV_THR 0x4 +6% / +60 mV LDO3_PG_WINDOWLDO3_OV_THR 0x4 0x4 +6% / +60 mV +6% / +60 mV LDO3_UV_THR 0x4 -6% / -60 mV LDO3_UV_THR 0x4 0x4 -6% / -60 mV -6% / -60 mV LDO4_PG_WINDOW LDO4_OV_THR 0x4 +6% / +60 mV LDO4_PG_WINDOWLDO4_OV_THR 0x4 0x4 +6% / +60 mV +6% / +60 mV LDO4_UV_THR 0x4 -6% / -60 mV LDO4_UV_THR 0x4 0x4 -6% / -60 mV -6% / -60 mV VCCA Settings These settings detail the default monitoring enabled on VCCA. All these settings can be changed though I2C after startup. VCCA NVM Settings Register Name Field Name TPS65931211-Q1 Value Description VCCA_VMON_CTRL VMON_DEGLITCH_SEL 0x1 20 us VCCA_VMON_EN 0x0 Disabled; OV and UV comparators. VCCA_PG_WINDOW VCCA_OV_THR 0x7 +10% VCCA_UV_THR 0x7 -10% VCCA_PG_SET 0x1 5.0 V GENERAL_REG_1 FAST_VCCA_OVP 0x0 slow, 4us deglitch filter enabled GENERAL_REG_3 LPM_EN_DISABLES_VCCA_VMON 0x1 VCCA_VMON enabled if VCCA_VMON_EN=1 and LPM_EN=0 VCCA Settings These settings detail the default monitoring enabled on VCCA. All these settings can be changed though I2C after startup. VCCA NVM Settings Register Name Field Name TPS65931211-Q1 Value Description VCCA_VMON_CTRL VMON_DEGLITCH_SEL 0x1 20 us VCCA_VMON_EN 0x0 Disabled; OV and UV comparators. VCCA_PG_WINDOW VCCA_OV_THR 0x7 +10% VCCA_UV_THR 0x7 -10% VCCA_PG_SET 0x1 5.0 V GENERAL_REG_1 FAST_VCCA_OVP 0x0 slow, 4us deglitch filter enabled GENERAL_REG_3 LPM_EN_DISABLES_VCCA_VMON 0x1 VCCA_VMON enabled if VCCA_VMON_EN=1 and LPM_EN=0 These settings detail the default monitoring enabled on VCCA. All these settings can be changed though I2C after startup. VCCA NVM Settings Register Name Field Name TPS65931211-Q1 Value Description VCCA_VMON_CTRL VMON_DEGLITCH_SEL 0x1 20 us VCCA_VMON_EN 0x0 Disabled; OV and UV comparators. VCCA_PG_WINDOW VCCA_OV_THR 0x7 +10% VCCA_UV_THR 0x7 -10% VCCA_PG_SET 0x1 5.0 V GENERAL_REG_1 FAST_VCCA_OVP 0x0 slow, 4us deglitch filter enabled GENERAL_REG_3 LPM_EN_DISABLES_VCCA_VMON 0x1 VCCA_VMON enabled if VCCA_VMON_EN=1 and LPM_EN=0 These settings detail the default monitoring enabled on VCCA. All these settings can be changed though I2C after startup.2 VCCA NVM Settings Register Name Field Name TPS65931211-Q1 Value Description VCCA_VMON_CTRL VMON_DEGLITCH_SEL 0x1 20 us VCCA_VMON_EN 0x0 Disabled; OV and UV comparators. VCCA_PG_WINDOW VCCA_OV_THR 0x7 +10% VCCA_UV_THR 0x7 -10% VCCA_PG_SET 0x1 5.0 V GENERAL_REG_1 FAST_VCCA_OVP 0x0 slow, 4us deglitch filter enabled GENERAL_REG_3 LPM_EN_DISABLES_VCCA_VMON 0x1 VCCA_VMON enabled if VCCA_VMON_EN=1 and LPM_EN=0 VCCA NVM Settings Register Name Field Name TPS65931211-Q1 Value Description VCCA_VMON_CTRL VMON_DEGLITCH_SEL 0x1 20 us VCCA_VMON_EN 0x0 Disabled; OV and UV comparators. VCCA_PG_WINDOW VCCA_OV_THR 0x7 +10% VCCA_UV_THR 0x7 -10% VCCA_PG_SET 0x1 5.0 V GENERAL_REG_1 FAST_VCCA_OVP 0x0 slow, 4us deglitch filter enabled GENERAL_REG_3 LPM_EN_DISABLES_VCCA_VMON 0x1 VCCA_VMON enabled if VCCA_VMON_EN=1 and LPM_EN=0 Register Name Field Name TPS65931211-Q1 Value Description Register Name Field Name TPS65931211-Q1 Register NameField Name TPS65931211-Q1 TPS65931211-Q1 Value Description ValueDescription VCCA_VMON_CTRL VMON_DEGLITCH_SEL 0x1 20 us VCCA_VMON_EN 0x0 Disabled; OV and UV comparators. VCCA_PG_WINDOW VCCA_OV_THR 0x7 +10% VCCA_UV_THR 0x7 -10% VCCA_PG_SET 0x1 5.0 V GENERAL_REG_1 FAST_VCCA_OVP 0x0 slow, 4us deglitch filter enabled GENERAL_REG_3 LPM_EN_DISABLES_VCCA_VMON 0x1 VCCA_VMON enabled if VCCA_VMON_EN=1 and LPM_EN=0 VCCA_VMON_CTRL VMON_DEGLITCH_SEL 0x1 20 us VCCA_VMON_CTRLVMON_DEGLITCH_SEL 0x1 0x1 20 us 20 us VCCA_VMON_EN 0x0 Disabled; OV and UV comparators. VCCA_VMON_EN 0x0 0x0 Disabled; OV and UV comparators. Disabled; OV and UV comparators. VCCA_PG_WINDOW VCCA_OV_THR 0x7 +10% VCCA_PG_WINDOWVCCA_OV_THR 0x7 0x7 +10% +10% VCCA_UV_THR 0x7 -10% VCCA_UV_THR 0x7 0x7 -10% -10% VCCA_PG_SET 0x1 5.0 V VCCA_PG_SET 0x1 0x1 5.0 V 5.0 V GENERAL_REG_1 FAST_VCCA_OVP 0x0 slow, 4us deglitch filter enabled GENERAL_REG_1FAST_VCCA_OVP 0x0 0x0 slow, 4us deglitch filter enabled slow, 4us deglitch filter enabled GENERAL_REG_3 LPM_EN_DISABLES_VCCA_VMON 0x1 VCCA_VMON enabled if VCCA_VMON_EN=1 and LPM_EN=0 GENERAL_REG_3LPM_EN_DISABLES_VCCA_VMON 0x1 0x1 VCCA_VMON enabled if VCCA_VMON_EN=1 and LPM_EN=0 VCCA_VMON enabled if VCCA_VMON_EN=1 and LPM_EN=0 GPIO Settings These settings detail the default configurations of the GPIO rails. Note that the contents of the GPIOx_SEL field determine which other fields in the GPIOx_CONF and GPIO_OUT_x registers are applicable. To understand which NVM fields apply to each GPIOx_SEL option, see the Digital Signal Descriptions section in TPS6593-Q1 data sheet. GPIO NVM Settings Register Name Field Name TPS65931211-Q1 Value Description GPIO1_CONF GPIO1_OD 0x0 Push-pull output GPIO1_DIR 0x0 Input GPIO1_SEL 0x1 SCL_I2C2/CS_SPI GPIO1_PU_SEL 0x0 Pull-down resistor selected GPIO1_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor. GPIO1_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO2_CONF GPIO2_OD 0x0 Push-pull output GPIO2_DIR 0x0 Input GPIO2_SEL 0x2 SDA_I2C2/SDO_SPI GPIO2_PU_SEL 0x0 Pull-down resistor selected GPIO2_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor. GPIO2_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO3_CONF GPIO3_OD 0x1 Open-drain output GPIO3_DIR 0x0 Input GPIO3_SEL 0x5 NSLEEP2 GPIO3_PU_SEL 0x0 Pull-down resistor selected GPIO3_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO3_DEGLITCH_EN 0x1 8 us deglitch time. GPIO4_CONF GPIO4_OD 0x0 Push-pull output GPIO4_DIR 0x1 Output GPIO4_SEL 0x0 GPIO4 GPIO4_PU_SEL 0x0 Pull-down resistor selected GPIO4_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor. GPIO4_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO5_CONF GPIO5_OD 0x1 Open-drain output GPIO5_DIR 0x0 Input GPIO5_SEL 0x0 GPIO5 GPIO5_PU_SEL 0x0 Pull-down resistor selected GPIO5_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO5_DEGLITCH_EN 0x1 8 us deglitch time. GPIO6_CONF GPIO6_OD 0x0 Push-pull output GPIO6_DIR 0x0 Input GPIO6_SEL 0x0 GPIO6 GPIO6_PU_SEL 0x0 Pull-down resistor selected GPIO6_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO6_DEGLITCH_EN 0x1 8 us deglitch time. GPIO7_CONF GPIO7_OD 0x1 Open-drain output GPIO7_DIR 0x0 Input GPIO7_SEL 0x1 NERR_MCU GPIO7_PU_SEL 0x0 Pull-down resistor selected GPIO7_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO7_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO8_CONF GPIO8_OD 0x1 Open-drain output GPIO8_DIR 0x0 Input GPIO8_SEL 0x3 DISABLE_WDOG GPIO8_PU_SEL 0x0 Pull-down resistor selected GPIO8_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO8_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO9_CONF GPIO9_OD 0x1 Open-drain output GPIO9_DIR 0x0 Input GPIO9_SEL 0x0 GPIO9 GPIO9_PU_SEL 0x0 Pull-down resistor selected GPIO9_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO9_DEGLITCH_EN 0x1 8 us deglitch time. GPIO10_CONF GPIO10_OD 0x1 Open-drain output GPIO10_DIR 0x0 Input GPIO10_SEL 0x0 GPIO10 GPIO10_PU_SEL 0x0 Pull-down resistor selected GPIO10_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO10_DEGLITCH_EN 0x1 8 us deglitch time. GPIO11_CONF GPIO11_OD 0x1 Open-drain output GPIO11_DIR 0x0 Input GPIO11_SEL 0x0 GPIO11 GPIO11_PU_SEL 0x0 Pull-down resistor selected GPIO11_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO11_DEGLITCH_EN 0x1 8 us deglitch time. NPWRON_CONF NPWRON_SEL 0x0 ENABLE ENABLE_PU_SEL 0x0 Pull-down resistor selected ENABLE_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. ENABLE_DEGLITCH_EN 0x1 8 us deglitch time when ENABLE, 50 ms deglitch time when NPWRON. ENABLE_POL 0x0 Active high NRSTOUT_OD 0x1 Open-drain output GPIO_OUT_1 GPIO1_OUT 0x0 Low GPIO2_OUT 0x0 Low GPIO3_OUT 0x0 Low GPIO4_OUT 0x0 Low GPIO5_OUT 0x0 Low GPIO6_OUT 0x0 Low GPIO7_OUT 0x0 Low GPIO8_OUT 0x0 Low GPIO_OUT_2 GPIO9_OUT 0x0 Low GPIO10_OUT 0x0 Low GPIO11_OUT 0x0 Low GPIO Settings These settings detail the default configurations of the GPIO rails. Note that the contents of the GPIOx_SEL field determine which other fields in the GPIOx_CONF and GPIO_OUT_x registers are applicable. To understand which NVM fields apply to each GPIOx_SEL option, see the Digital Signal Descriptions section in TPS6593-Q1 data sheet. GPIO NVM Settings Register Name Field Name TPS65931211-Q1 Value Description GPIO1_CONF GPIO1_OD 0x0 Push-pull output GPIO1_DIR 0x0 Input GPIO1_SEL 0x1 SCL_I2C2/CS_SPI GPIO1_PU_SEL 0x0 Pull-down resistor selected GPIO1_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor. GPIO1_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO2_CONF GPIO2_OD 0x0 Push-pull output GPIO2_DIR 0x0 Input GPIO2_SEL 0x2 SDA_I2C2/SDO_SPI GPIO2_PU_SEL 0x0 Pull-down resistor selected GPIO2_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor. GPIO2_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO3_CONF GPIO3_OD 0x1 Open-drain output GPIO3_DIR 0x0 Input GPIO3_SEL 0x5 NSLEEP2 GPIO3_PU_SEL 0x0 Pull-down resistor selected GPIO3_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO3_DEGLITCH_EN 0x1 8 us deglitch time. GPIO4_CONF GPIO4_OD 0x0 Push-pull output GPIO4_DIR 0x1 Output GPIO4_SEL 0x0 GPIO4 GPIO4_PU_SEL 0x0 Pull-down resistor selected GPIO4_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor. GPIO4_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO5_CONF GPIO5_OD 0x1 Open-drain output GPIO5_DIR 0x0 Input GPIO5_SEL 0x0 GPIO5 GPIO5_PU_SEL 0x0 Pull-down resistor selected GPIO5_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO5_DEGLITCH_EN 0x1 8 us deglitch time. GPIO6_CONF GPIO6_OD 0x0 Push-pull output GPIO6_DIR 0x0 Input GPIO6_SEL 0x0 GPIO6 GPIO6_PU_SEL 0x0 Pull-down resistor selected GPIO6_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO6_DEGLITCH_EN 0x1 8 us deglitch time. GPIO7_CONF GPIO7_OD 0x1 Open-drain output GPIO7_DIR 0x0 Input GPIO7_SEL 0x1 NERR_MCU GPIO7_PU_SEL 0x0 Pull-down resistor selected GPIO7_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO7_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO8_CONF GPIO8_OD 0x1 Open-drain output GPIO8_DIR 0x0 Input GPIO8_SEL 0x3 DISABLE_WDOG GPIO8_PU_SEL 0x0 Pull-down resistor selected GPIO8_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO8_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO9_CONF GPIO9_OD 0x1 Open-drain output GPIO9_DIR 0x0 Input GPIO9_SEL 0x0 GPIO9 GPIO9_PU_SEL 0x0 Pull-down resistor selected GPIO9_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO9_DEGLITCH_EN 0x1 8 us deglitch time. GPIO10_CONF GPIO10_OD 0x1 Open-drain output GPIO10_DIR 0x0 Input GPIO10_SEL 0x0 GPIO10 GPIO10_PU_SEL 0x0 Pull-down resistor selected GPIO10_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO10_DEGLITCH_EN 0x1 8 us deglitch time. GPIO11_CONF GPIO11_OD 0x1 Open-drain output GPIO11_DIR 0x0 Input GPIO11_SEL 0x0 GPIO11 GPIO11_PU_SEL 0x0 Pull-down resistor selected GPIO11_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO11_DEGLITCH_EN 0x1 8 us deglitch time. NPWRON_CONF NPWRON_SEL 0x0 ENABLE ENABLE_PU_SEL 0x0 Pull-down resistor selected ENABLE_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. ENABLE_DEGLITCH_EN 0x1 8 us deglitch time when ENABLE, 50 ms deglitch time when NPWRON. ENABLE_POL 0x0 Active high NRSTOUT_OD 0x1 Open-drain output GPIO_OUT_1 GPIO1_OUT 0x0 Low GPIO2_OUT 0x0 Low GPIO3_OUT 0x0 Low GPIO4_OUT 0x0 Low GPIO5_OUT 0x0 Low GPIO6_OUT 0x0 Low GPIO7_OUT 0x0 Low GPIO8_OUT 0x0 Low GPIO_OUT_2 GPIO9_OUT 0x0 Low GPIO10_OUT 0x0 Low GPIO11_OUT 0x0 Low These settings detail the default configurations of the GPIO rails. Note that the contents of the GPIOx_SEL field determine which other fields in the GPIOx_CONF and GPIO_OUT_x registers are applicable. To understand which NVM fields apply to each GPIOx_SEL option, see the Digital Signal Descriptions section in TPS6593-Q1 data sheet. GPIO NVM Settings Register Name Field Name TPS65931211-Q1 Value Description GPIO1_CONF GPIO1_OD 0x0 Push-pull output GPIO1_DIR 0x0 Input GPIO1_SEL 0x1 SCL_I2C2/CS_SPI GPIO1_PU_SEL 0x0 Pull-down resistor selected GPIO1_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor. GPIO1_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO2_CONF GPIO2_OD 0x0 Push-pull output GPIO2_DIR 0x0 Input GPIO2_SEL 0x2 SDA_I2C2/SDO_SPI GPIO2_PU_SEL 0x0 Pull-down resistor selected GPIO2_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor. GPIO2_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO3_CONF GPIO3_OD 0x1 Open-drain output GPIO3_DIR 0x0 Input GPIO3_SEL 0x5 NSLEEP2 GPIO3_PU_SEL 0x0 Pull-down resistor selected GPIO3_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO3_DEGLITCH_EN 0x1 8 us deglitch time. GPIO4_CONF GPIO4_OD 0x0 Push-pull output GPIO4_DIR 0x1 Output GPIO4_SEL 0x0 GPIO4 GPIO4_PU_SEL 0x0 Pull-down resistor selected GPIO4_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor. GPIO4_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO5_CONF GPIO5_OD 0x1 Open-drain output GPIO5_DIR 0x0 Input GPIO5_SEL 0x0 GPIO5 GPIO5_PU_SEL 0x0 Pull-down resistor selected GPIO5_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO5_DEGLITCH_EN 0x1 8 us deglitch time. GPIO6_CONF GPIO6_OD 0x0 Push-pull output GPIO6_DIR 0x0 Input GPIO6_SEL 0x0 GPIO6 GPIO6_PU_SEL 0x0 Pull-down resistor selected GPIO6_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO6_DEGLITCH_EN 0x1 8 us deglitch time. GPIO7_CONF GPIO7_OD 0x1 Open-drain output GPIO7_DIR 0x0 Input GPIO7_SEL 0x1 NERR_MCU GPIO7_PU_SEL 0x0 Pull-down resistor selected GPIO7_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO7_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO8_CONF GPIO8_OD 0x1 Open-drain output GPIO8_DIR 0x0 Input GPIO8_SEL 0x3 DISABLE_WDOG GPIO8_PU_SEL 0x0 Pull-down resistor selected GPIO8_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO8_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO9_CONF GPIO9_OD 0x1 Open-drain output GPIO9_DIR 0x0 Input GPIO9_SEL 0x0 GPIO9 GPIO9_PU_SEL 0x0 Pull-down resistor selected GPIO9_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO9_DEGLITCH_EN 0x1 8 us deglitch time. GPIO10_CONF GPIO10_OD 0x1 Open-drain output GPIO10_DIR 0x0 Input GPIO10_SEL 0x0 GPIO10 GPIO10_PU_SEL 0x0 Pull-down resistor selected GPIO10_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO10_DEGLITCH_EN 0x1 8 us deglitch time. GPIO11_CONF GPIO11_OD 0x1 Open-drain output GPIO11_DIR 0x0 Input GPIO11_SEL 0x0 GPIO11 GPIO11_PU_SEL 0x0 Pull-down resistor selected GPIO11_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO11_DEGLITCH_EN 0x1 8 us deglitch time. NPWRON_CONF NPWRON_SEL 0x0 ENABLE ENABLE_PU_SEL 0x0 Pull-down resistor selected ENABLE_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. ENABLE_DEGLITCH_EN 0x1 8 us deglitch time when ENABLE, 50 ms deglitch time when NPWRON. ENABLE_POL 0x0 Active high NRSTOUT_OD 0x1 Open-drain output GPIO_OUT_1 GPIO1_OUT 0x0 Low GPIO2_OUT 0x0 Low GPIO3_OUT 0x0 Low GPIO4_OUT 0x0 Low GPIO5_OUT 0x0 Low GPIO6_OUT 0x0 Low GPIO7_OUT 0x0 Low GPIO8_OUT 0x0 Low GPIO_OUT_2 GPIO9_OUT 0x0 Low GPIO10_OUT 0x0 Low GPIO11_OUT 0x0 Low These settings detail the default configurations of the GPIO rails. Note that the contents of the GPIOx_SEL field determine which other fields in the GPIOx_CONF and GPIO_OUT_x registers are applicable. To understand which NVM fields apply to each GPIOx_SEL option, see the Digital Signal Descriptions section in TPS6593-Q1 data sheet.Digital Signal Descriptions GPIO NVM Settings Register Name Field Name TPS65931211-Q1 Value Description GPIO1_CONF GPIO1_OD 0x0 Push-pull output GPIO1_DIR 0x0 Input GPIO1_SEL 0x1 SCL_I2C2/CS_SPI GPIO1_PU_SEL 0x0 Pull-down resistor selected GPIO1_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor. GPIO1_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO2_CONF GPIO2_OD 0x0 Push-pull output GPIO2_DIR 0x0 Input GPIO2_SEL 0x2 SDA_I2C2/SDO_SPI GPIO2_PU_SEL 0x0 Pull-down resistor selected GPIO2_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor. GPIO2_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO3_CONF GPIO3_OD 0x1 Open-drain output GPIO3_DIR 0x0 Input GPIO3_SEL 0x5 NSLEEP2 GPIO3_PU_SEL 0x0 Pull-down resistor selected GPIO3_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO3_DEGLITCH_EN 0x1 8 us deglitch time. GPIO4_CONF GPIO4_OD 0x0 Push-pull output GPIO4_DIR 0x1 Output GPIO4_SEL 0x0 GPIO4 GPIO4_PU_SEL 0x0 Pull-down resistor selected GPIO4_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor. GPIO4_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO5_CONF GPIO5_OD 0x1 Open-drain output GPIO5_DIR 0x0 Input GPIO5_SEL 0x0 GPIO5 GPIO5_PU_SEL 0x0 Pull-down resistor selected GPIO5_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO5_DEGLITCH_EN 0x1 8 us deglitch time. GPIO6_CONF GPIO6_OD 0x0 Push-pull output GPIO6_DIR 0x0 Input GPIO6_SEL 0x0 GPIO6 GPIO6_PU_SEL 0x0 Pull-down resistor selected GPIO6_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO6_DEGLITCH_EN 0x1 8 us deglitch time. GPIO7_CONF GPIO7_OD 0x1 Open-drain output GPIO7_DIR 0x0 Input GPIO7_SEL 0x1 NERR_MCU GPIO7_PU_SEL 0x0 Pull-down resistor selected GPIO7_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO7_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO8_CONF GPIO8_OD 0x1 Open-drain output GPIO8_DIR 0x0 Input GPIO8_SEL 0x3 DISABLE_WDOG GPIO8_PU_SEL 0x0 Pull-down resistor selected GPIO8_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO8_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO9_CONF GPIO9_OD 0x1 Open-drain output GPIO9_DIR 0x0 Input GPIO9_SEL 0x0 GPIO9 GPIO9_PU_SEL 0x0 Pull-down resistor selected GPIO9_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO9_DEGLITCH_EN 0x1 8 us deglitch time. GPIO10_CONF GPIO10_OD 0x1 Open-drain output GPIO10_DIR 0x0 Input GPIO10_SEL 0x0 GPIO10 GPIO10_PU_SEL 0x0 Pull-down resistor selected GPIO10_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO10_DEGLITCH_EN 0x1 8 us deglitch time. GPIO11_CONF GPIO11_OD 0x1 Open-drain output GPIO11_DIR 0x0 Input GPIO11_SEL 0x0 GPIO11 GPIO11_PU_SEL 0x0 Pull-down resistor selected GPIO11_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO11_DEGLITCH_EN 0x1 8 us deglitch time. NPWRON_CONF NPWRON_SEL 0x0 ENABLE ENABLE_PU_SEL 0x0 Pull-down resistor selected ENABLE_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. ENABLE_DEGLITCH_EN 0x1 8 us deglitch time when ENABLE, 50 ms deglitch time when NPWRON. ENABLE_POL 0x0 Active high NRSTOUT_OD 0x1 Open-drain output GPIO_OUT_1 GPIO1_OUT 0x0 Low GPIO2_OUT 0x0 Low GPIO3_OUT 0x0 Low GPIO4_OUT 0x0 Low GPIO5_OUT 0x0 Low GPIO6_OUT 0x0 Low GPIO7_OUT 0x0 Low GPIO8_OUT 0x0 Low GPIO_OUT_2 GPIO9_OUT 0x0 Low GPIO10_OUT 0x0 Low GPIO11_OUT 0x0 Low GPIO NVM Settings Register Name Field Name TPS65931211-Q1 Value Description GPIO1_CONF GPIO1_OD 0x0 Push-pull output GPIO1_DIR 0x0 Input GPIO1_SEL 0x1 SCL_I2C2/CS_SPI GPIO1_PU_SEL 0x0 Pull-down resistor selected GPIO1_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor. GPIO1_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO2_CONF GPIO2_OD 0x0 Push-pull output GPIO2_DIR 0x0 Input GPIO2_SEL 0x2 SDA_I2C2/SDO_SPI GPIO2_PU_SEL 0x0 Pull-down resistor selected GPIO2_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor. GPIO2_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO3_CONF GPIO3_OD 0x1 Open-drain output GPIO3_DIR 0x0 Input GPIO3_SEL 0x5 NSLEEP2 GPIO3_PU_SEL 0x0 Pull-down resistor selected GPIO3_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO3_DEGLITCH_EN 0x1 8 us deglitch time. GPIO4_CONF GPIO4_OD 0x0 Push-pull output GPIO4_DIR 0x1 Output GPIO4_SEL 0x0 GPIO4 GPIO4_PU_SEL 0x0 Pull-down resistor selected GPIO4_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor. GPIO4_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO5_CONF GPIO5_OD 0x1 Open-drain output GPIO5_DIR 0x0 Input GPIO5_SEL 0x0 GPIO5 GPIO5_PU_SEL 0x0 Pull-down resistor selected GPIO5_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO5_DEGLITCH_EN 0x1 8 us deglitch time. GPIO6_CONF GPIO6_OD 0x0 Push-pull output GPIO6_DIR 0x0 Input GPIO6_SEL 0x0 GPIO6 GPIO6_PU_SEL 0x0 Pull-down resistor selected GPIO6_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO6_DEGLITCH_EN 0x1 8 us deglitch time. GPIO7_CONF GPIO7_OD 0x1 Open-drain output GPIO7_DIR 0x0 Input GPIO7_SEL 0x1 NERR_MCU GPIO7_PU_SEL 0x0 Pull-down resistor selected GPIO7_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO7_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO8_CONF GPIO8_OD 0x1 Open-drain output GPIO8_DIR 0x0 Input GPIO8_SEL 0x3 DISABLE_WDOG GPIO8_PU_SEL 0x0 Pull-down resistor selected GPIO8_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO8_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO9_CONF GPIO9_OD 0x1 Open-drain output GPIO9_DIR 0x0 Input GPIO9_SEL 0x0 GPIO9 GPIO9_PU_SEL 0x0 Pull-down resistor selected GPIO9_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO9_DEGLITCH_EN 0x1 8 us deglitch time. GPIO10_CONF GPIO10_OD 0x1 Open-drain output GPIO10_DIR 0x0 Input GPIO10_SEL 0x0 GPIO10 GPIO10_PU_SEL 0x0 Pull-down resistor selected GPIO10_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO10_DEGLITCH_EN 0x1 8 us deglitch time. GPIO11_CONF GPIO11_OD 0x1 Open-drain output GPIO11_DIR 0x0 Input GPIO11_SEL 0x0 GPIO11 GPIO11_PU_SEL 0x0 Pull-down resistor selected GPIO11_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO11_DEGLITCH_EN 0x1 8 us deglitch time. NPWRON_CONF NPWRON_SEL 0x0 ENABLE ENABLE_PU_SEL 0x0 Pull-down resistor selected ENABLE_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. ENABLE_DEGLITCH_EN 0x1 8 us deglitch time when ENABLE, 50 ms deglitch time when NPWRON. ENABLE_POL 0x0 Active high NRSTOUT_OD 0x1 Open-drain output GPIO_OUT_1 GPIO1_OUT 0x0 Low GPIO2_OUT 0x0 Low GPIO3_OUT 0x0 Low GPIO4_OUT 0x0 Low GPIO5_OUT 0x0 Low GPIO6_OUT 0x0 Low GPIO7_OUT 0x0 Low GPIO8_OUT 0x0 Low GPIO_OUT_2 GPIO9_OUT 0x0 Low GPIO10_OUT 0x0 Low GPIO11_OUT 0x0 Low Register Name Field Name TPS65931211-Q1 Value Description Register Name Field Name TPS65931211-Q1 Register NameField Name TPS65931211-Q1 TPS65931211-Q1 Value Description ValueDescription GPIO1_CONF GPIO1_OD 0x0 Push-pull output GPIO1_DIR 0x0 Input GPIO1_SEL 0x1 SCL_I2C2/CS_SPI GPIO1_PU_SEL 0x0 Pull-down resistor selected GPIO1_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor. GPIO1_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO2_CONF GPIO2_OD 0x0 Push-pull output GPIO2_DIR 0x0 Input GPIO2_SEL 0x2 SDA_I2C2/SDO_SPI GPIO2_PU_SEL 0x0 Pull-down resistor selected GPIO2_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor. GPIO2_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO3_CONF GPIO3_OD 0x1 Open-drain output GPIO3_DIR 0x0 Input GPIO3_SEL 0x5 NSLEEP2 GPIO3_PU_SEL 0x0 Pull-down resistor selected GPIO3_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO3_DEGLITCH_EN 0x1 8 us deglitch time. GPIO4_CONF GPIO4_OD 0x0 Push-pull output GPIO4_DIR 0x1 Output GPIO4_SEL 0x0 GPIO4 GPIO4_PU_SEL 0x0 Pull-down resistor selected GPIO4_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor. GPIO4_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO5_CONF GPIO5_OD 0x1 Open-drain output GPIO5_DIR 0x0 Input GPIO5_SEL 0x0 GPIO5 GPIO5_PU_SEL 0x0 Pull-down resistor selected GPIO5_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO5_DEGLITCH_EN 0x1 8 us deglitch time. GPIO6_CONF GPIO6_OD 0x0 Push-pull output GPIO6_DIR 0x0 Input GPIO6_SEL 0x0 GPIO6 GPIO6_PU_SEL 0x0 Pull-down resistor selected GPIO6_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO6_DEGLITCH_EN 0x1 8 us deglitch time. GPIO7_CONF GPIO7_OD 0x1 Open-drain output GPIO7_DIR 0x0 Input GPIO7_SEL 0x1 NERR_MCU GPIO7_PU_SEL 0x0 Pull-down resistor selected GPIO7_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO7_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO8_CONF GPIO8_OD 0x1 Open-drain output GPIO8_DIR 0x0 Input GPIO8_SEL 0x3 DISABLE_WDOG GPIO8_PU_SEL 0x0 Pull-down resistor selected GPIO8_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO8_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO9_CONF GPIO9_OD 0x1 Open-drain output GPIO9_DIR 0x0 Input GPIO9_SEL 0x0 GPIO9 GPIO9_PU_SEL 0x0 Pull-down resistor selected GPIO9_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO9_DEGLITCH_EN 0x1 8 us deglitch time. GPIO10_CONF GPIO10_OD 0x1 Open-drain output GPIO10_DIR 0x0 Input GPIO10_SEL 0x0 GPIO10 GPIO10_PU_SEL 0x0 Pull-down resistor selected GPIO10_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO10_DEGLITCH_EN 0x1 8 us deglitch time. GPIO11_CONF GPIO11_OD 0x1 Open-drain output GPIO11_DIR 0x0 Input GPIO11_SEL 0x0 GPIO11 GPIO11_PU_SEL 0x0 Pull-down resistor selected GPIO11_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO11_DEGLITCH_EN 0x1 8 us deglitch time. NPWRON_CONF NPWRON_SEL 0x0 ENABLE ENABLE_PU_SEL 0x0 Pull-down resistor selected ENABLE_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. ENABLE_DEGLITCH_EN 0x1 8 us deglitch time when ENABLE, 50 ms deglitch time when NPWRON. ENABLE_POL 0x0 Active high NRSTOUT_OD 0x1 Open-drain output GPIO_OUT_1 GPIO1_OUT 0x0 Low GPIO2_OUT 0x0 Low GPIO3_OUT 0x0 Low GPIO4_OUT 0x0 Low GPIO5_OUT 0x0 Low GPIO6_OUT 0x0 Low GPIO7_OUT 0x0 Low GPIO8_OUT 0x0 Low GPIO_OUT_2 GPIO9_OUT 0x0 Low GPIO10_OUT 0x0 Low GPIO11_OUT 0x0 Low GPIO1_CONF GPIO1_OD 0x0 Push-pull output GPIO1_CONFGPIO1_OD 0x0 0x0 Push-pull output Push-pull output GPIO1_DIR 0x0 Input GPIO1_DIR 0x0 0x0 Input Input GPIO1_SEL 0x1 SCL_I2C2/CS_SPI GPIO1_SEL 0x1 0x1 SCL_I2C2/CS_SPI SCL_I2C2/CS_SPI GPIO1_PU_SEL 0x0 Pull-down resistor selected GPIO1_PU_SEL 0x0 0x0 Pull-down resistor selected Pull-down resistor selected GPIO1_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor. GPIO1_PU_PD_EN 0x0 0x0 Disabled; Pull-up/pull-down resistor. Disabled; Pull-up/pull-down resistor. GPIO1_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO1_DEGLITCH_EN 0x0 0x0 No deglitch, only synchronization. No deglitch, only synchronization. GPIO2_CONF GPIO2_OD 0x0 Push-pull output GPIO2_CONFGPIO2_OD 0x0 0x0 Push-pull output Push-pull output GPIO2_DIR 0x0 Input GPIO2_DIR 0x0 0x0 Input Input GPIO2_SEL 0x2 SDA_I2C2/SDO_SPI GPIO2_SEL 0x2 0x2 SDA_I2C2/SDO_SPI SDA_I2C2/SDO_SPI GPIO2_PU_SEL 0x0 Pull-down resistor selected GPIO2_PU_SEL 0x0 0x0 Pull-down resistor selected Pull-down resistor selected GPIO2_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor. GPIO2_PU_PD_EN 0x0 0x0 Disabled; Pull-up/pull-down resistor. Disabled; Pull-up/pull-down resistor. GPIO2_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO2_DEGLITCH_EN 0x0 0x0 No deglitch, only synchronization. No deglitch, only synchronization. GPIO3_CONF GPIO3_OD 0x1 Open-drain output GPIO3_CONFGPIO3_OD 0x1 0x1 Open-drain output Open-drain output GPIO3_DIR 0x0 Input GPIO3_DIR 0x0 0x0 Input Input GPIO3_SEL 0x5 NSLEEP2 GPIO3_SEL 0x5 0x5 NSLEEP2 NSLEEP2 GPIO3_PU_SEL 0x0 Pull-down resistor selected GPIO3_PU_SEL 0x0 0x0 Pull-down resistor selected Pull-down resistor selected GPIO3_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO3_PU_PD_EN 0x1 0x1 Enabled; Pull-up/pull-down resistor. Enabled; Pull-up/pull-down resistor. GPIO3_DEGLITCH_EN 0x1 8 us deglitch time. GPIO3_DEGLITCH_EN 0x1 0x1 8 us deglitch time. 8 us deglitch time. GPIO4_CONF GPIO4_OD 0x0 Push-pull output GPIO4_CONFGPIO4_OD 0x0 0x0 Push-pull output Push-pull output GPIO4_DIR 0x1 Output GPIO4_DIR 0x1 0x1 Output Output GPIO4_SEL 0x0 GPIO4 GPIO4_SEL 0x0 0x0 GPIO4 GPIO4 GPIO4_PU_SEL 0x0 Pull-down resistor selected GPIO4_PU_SEL 0x0 0x0 Pull-down resistor selected Pull-down resistor selected GPIO4_PU_PD_EN 0x0 Disabled; Pull-up/pull-down resistor. GPIO4_PU_PD_EN 0x0 0x0 Disabled; Pull-up/pull-down resistor. Disabled; Pull-up/pull-down resistor. GPIO4_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO4_DEGLITCH_EN 0x0 0x0 No deglitch, only synchronization. No deglitch, only synchronization. GPIO5_CONF GPIO5_OD 0x1 Open-drain output GPIO5_CONFGPIO5_OD 0x1 0x1 Open-drain output Open-drain output GPIO5_DIR 0x0 Input GPIO5_DIR 0x0 0x0 Input Input GPIO5_SEL 0x0 GPIO5 GPIO5_SEL 0x0 0x0 GPIO5 GPIO5 GPIO5_PU_SEL 0x0 Pull-down resistor selected GPIO5_PU_SEL 0x0 0x0 Pull-down resistor selected Pull-down resistor selected GPIO5_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO5_PU_PD_EN 0x1 0x1 Enabled; Pull-up/pull-down resistor. Enabled; Pull-up/pull-down resistor. GPIO5_DEGLITCH_EN 0x1 8 us deglitch time. GPIO5_DEGLITCH_EN 0x1 0x1 8 us deglitch time. 8 us deglitch time. GPIO6_CONF GPIO6_OD 0x0 Push-pull output GPIO6_CONFGPIO6_OD 0x0 0x0 Push-pull output Push-pull output GPIO6_DIR 0x0 Input GPIO6_DIR 0x0 0x0 Input Input GPIO6_SEL 0x0 GPIO6 GPIO6_SEL 0x0 0x0 GPIO6 GPIO6 GPIO6_PU_SEL 0x0 Pull-down resistor selected GPIO6_PU_SEL 0x0 0x0 Pull-down resistor selected Pull-down resistor selected GPIO6_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO6_PU_PD_EN 0x1 0x1 Enabled; Pull-up/pull-down resistor. Enabled; Pull-up/pull-down resistor. GPIO6_DEGLITCH_EN 0x1 8 us deglitch time. GPIO6_DEGLITCH_EN 0x1 0x1 8 us deglitch time. 8 us deglitch time. GPIO7_CONF GPIO7_OD 0x1 Open-drain output GPIO7_CONFGPIO7_OD 0x1 0x1 Open-drain output Open-drain output GPIO7_DIR 0x0 Input GPIO7_DIR 0x0 0x0 Input Input GPIO7_SEL 0x1 NERR_MCU GPIO7_SEL 0x1 0x1 NERR_MCU NERR_MCU GPIO7_PU_SEL 0x0 Pull-down resistor selected GPIO7_PU_SEL 0x0 0x0 Pull-down resistor selected Pull-down resistor selected GPIO7_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO7_PU_PD_EN 0x1 0x1 Enabled; Pull-up/pull-down resistor. Enabled; Pull-up/pull-down resistor. GPIO7_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO7_DEGLITCH_EN 0x0 0x0 No deglitch, only synchronization. No deglitch, only synchronization. GPIO8_CONF GPIO8_OD 0x1 Open-drain output GPIO8_CONFGPIO8_OD 0x1 0x1 Open-drain output Open-drain output GPIO8_DIR 0x0 Input GPIO8_DIR 0x0 0x0 Input Input GPIO8_SEL 0x3 DISABLE_WDOG GPIO8_SEL 0x3 0x3 DISABLE_WDOG DISABLE_WDOG GPIO8_PU_SEL 0x0 Pull-down resistor selected GPIO8_PU_SEL 0x0 0x0 Pull-down resistor selected Pull-down resistor selected GPIO8_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO8_PU_PD_EN 0x1 0x1 Enabled; Pull-up/pull-down resistor. Enabled; Pull-up/pull-down resistor. GPIO8_DEGLITCH_EN 0x0 No deglitch, only synchronization. GPIO8_DEGLITCH_EN 0x0 0x0 No deglitch, only synchronization. No deglitch, only synchronization. GPIO9_CONF GPIO9_OD 0x1 Open-drain output GPIO9_CONFGPIO9_OD 0x1 0x1 Open-drain output Open-drain output GPIO9_DIR 0x0 Input GPIO9_DIR 0x0 0x0 Input Input GPIO9_SEL 0x0 GPIO9 GPIO9_SEL 0x0 0x0 GPIO9 GPIO9 GPIO9_PU_SEL 0x0 Pull-down resistor selected GPIO9_PU_SEL 0x0 0x0 Pull-down resistor selected Pull-down resistor selected GPIO9_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO9_PU_PD_EN 0x1 0x1 Enabled; Pull-up/pull-down resistor. Enabled; Pull-up/pull-down resistor. GPIO9_DEGLITCH_EN 0x1 8 us deglitch time. GPIO9_DEGLITCH_EN 0x1 0x1 8 us deglitch time. 8 us deglitch time. GPIO10_CONF GPIO10_OD 0x1 Open-drain output GPIO10_CONFGPIO10_OD 0x1 0x1 Open-drain output Open-drain output GPIO10_DIR 0x0 Input GPIO10_DIR 0x0 0x0 Input Input GPIO10_SEL 0x0 GPIO10 GPIO10_SEL 0x0 0x0 GPIO10 GPIO10 GPIO10_PU_SEL 0x0 Pull-down resistor selected GPIO10_PU_SEL 0x0 0x0 Pull-down resistor selected Pull-down resistor selected GPIO10_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO10_PU_PD_EN 0x1 0x1 Enabled; Pull-up/pull-down resistor. Enabled; Pull-up/pull-down resistor. GPIO10_DEGLITCH_EN 0x1 8 us deglitch time. GPIO10_DEGLITCH_EN 0x1 0x1 8 us deglitch time. 8 us deglitch time. GPIO11_CONF GPIO11_OD 0x1 Open-drain output GPIO11_CONFGPIO11_OD 0x1 0x1 Open-drain output Open-drain output GPIO11_DIR 0x0 Input GPIO11_DIR 0x0 0x0 Input Input GPIO11_SEL 0x0 GPIO11 GPIO11_SEL 0x0 0x0 GPIO11 GPIO11 GPIO11_PU_SEL 0x0 Pull-down resistor selected GPIO11_PU_SEL 0x0 0x0 Pull-down resistor selected Pull-down resistor selected GPIO11_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. GPIO11_PU_PD_EN 0x1 0x1 Enabled; Pull-up/pull-down resistor. Enabled; Pull-up/pull-down resistor. GPIO11_DEGLITCH_EN 0x1 8 us deglitch time. GPIO11_DEGLITCH_EN 0x1 0x1 8 us deglitch time. 8 us deglitch time. NPWRON_CONF NPWRON_SEL 0x0 ENABLE NPWRON_CONFNPWRON_SEL 0x0 0x0 ENABLE ENABLE ENABLE_PU_SEL 0x0 Pull-down resistor selected ENABLE_PU_SEL 0x0 0x0 Pull-down resistor selected Pull-down resistor selected ENABLE_PU_PD_EN 0x1 Enabled; Pull-up/pull-down resistor. ENABLE_PU_PD_EN 0x1 0x1 Enabled; Pull-up/pull-down resistor. Enabled; Pull-up/pull-down resistor. ENABLE_DEGLITCH_EN 0x1 8 us deglitch time when ENABLE, 50 ms deglitch time when NPWRON. ENABLE_DEGLITCH_EN 0x1 0x1 8 us deglitch time when ENABLE, 50 ms deglitch time when NPWRON. 8 us deglitch time when ENABLE, 50 ms deglitch time when NPWRON. ENABLE_POL 0x0 Active high ENABLE_POL 0x0 0x0 Active high Active high NRSTOUT_OD 0x1 Open-drain output NRSTOUT_OD 0x1 0x1 Open-drain output Open-drain output GPIO_OUT_1 GPIO1_OUT 0x0 Low GPIO_OUT_1GPIO1_OUT 0x0 0x0 Low Low GPIO2_OUT 0x0 Low GPIO2_OUT 0x0 0x0 Low Low GPIO3_OUT 0x0 Low GPIO3_OUT 0x0 0x0 Low Low GPIO4_OUT 0x0 Low GPIO4_OUT 0x0 0x0 Low Low GPIO5_OUT 0x0 Low GPIO5_OUT 0x0 0x0 Low Low GPIO6_OUT 0x0 Low GPIO6_OUT 0x0 0x0 Low Low GPIO7_OUT 0x0 Low GPIO7_OUT 0x0 0x0 Low Low GPIO8_OUT 0x0 Low GPIO8_OUT 0x0 0x0 Low Low GPIO_OUT_2 GPIO9_OUT 0x0 Low GPIO_OUT_2GPIO9_OUT 0x0 0x0 Low Low GPIO10_OUT 0x0 Low GPIO10_OUT 0x0 0x0 Low Low GPIO11_OUT 0x0 Low GPIO11_OUT 0x0 0x0 Low Low Finite State Machine (FSM) Settings These settings describe how the PMIC output rails are assigned to various system-level states. Also, the default trigger for each system-level state is described. All these settings can be changed though I2C after startup. FSM NVM Settings Register Name Field Name TPS65931211-Q1 Value Description RAIL_SEL_1 BUCK1_GRP_SEL 0x1 MCU rail group BUCK2_GRP_SEL 0x1 MCU rail group BUCK3_GRP_SEL 0x1 MCU rail group BUCK4_GRP_SEL 0x1 MCU rail group RAIL_SEL_2 BUCK5_GRP_SEL 0x1 MCU rail group LDO1_GRP_SEL 0x1 MCU rail group LDO2_GRP_SEL 0x3 OTHER rail group LDO3_GRP_SEL 0x1 MCU rail group RAIL_SEL_3 LDO4_GRP_SEL 0x1 MCU rail group VCCA_GRP_SEL 0x0 No group assigned FSM_TRIG_SEL_1 MCU_RAIL_TRIG 0x1 Orderly shutdown SOC_RAIL_TRIG 0x3 SOC power error OTHER_RAIL_TRIG 0x2 MCU power error SEVERE_ERR_TRIG 0x0 Immediate shutdown FSM_TRIG_SEL_2 MODERATE_ERR_TRIG 0x1 Orderly shutdown Finite State Machine (FSM) Settings These settings describe how the PMIC output rails are assigned to various system-level states. Also, the default trigger for each system-level state is described. All these settings can be changed though I2C after startup. FSM NVM Settings Register Name Field Name TPS65931211-Q1 Value Description RAIL_SEL_1 BUCK1_GRP_SEL 0x1 MCU rail group BUCK2_GRP_SEL 0x1 MCU rail group BUCK3_GRP_SEL 0x1 MCU rail group BUCK4_GRP_SEL 0x1 MCU rail group RAIL_SEL_2 BUCK5_GRP_SEL 0x1 MCU rail group LDO1_GRP_SEL 0x1 MCU rail group LDO2_GRP_SEL 0x3 OTHER rail group LDO3_GRP_SEL 0x1 MCU rail group RAIL_SEL_3 LDO4_GRP_SEL 0x1 MCU rail group VCCA_GRP_SEL 0x0 No group assigned FSM_TRIG_SEL_1 MCU_RAIL_TRIG 0x1 Orderly shutdown SOC_RAIL_TRIG 0x3 SOC power error OTHER_RAIL_TRIG 0x2 MCU power error SEVERE_ERR_TRIG 0x0 Immediate shutdown FSM_TRIG_SEL_2 MODERATE_ERR_TRIG 0x1 Orderly shutdown These settings describe how the PMIC output rails are assigned to various system-level states. Also, the default trigger for each system-level state is described. All these settings can be changed though I2C after startup. FSM NVM Settings Register Name Field Name TPS65931211-Q1 Value Description RAIL_SEL_1 BUCK1_GRP_SEL 0x1 MCU rail group BUCK2_GRP_SEL 0x1 MCU rail group BUCK3_GRP_SEL 0x1 MCU rail group BUCK4_GRP_SEL 0x1 MCU rail group RAIL_SEL_2 BUCK5_GRP_SEL 0x1 MCU rail group LDO1_GRP_SEL 0x1 MCU rail group LDO2_GRP_SEL 0x3 OTHER rail group LDO3_GRP_SEL 0x1 MCU rail group RAIL_SEL_3 LDO4_GRP_SEL 0x1 MCU rail group VCCA_GRP_SEL 0x0 No group assigned FSM_TRIG_SEL_1 MCU_RAIL_TRIG 0x1 Orderly shutdown SOC_RAIL_TRIG 0x3 SOC power error OTHER_RAIL_TRIG 0x2 MCU power error SEVERE_ERR_TRIG 0x0 Immediate shutdown FSM_TRIG_SEL_2 MODERATE_ERR_TRIG 0x1 Orderly shutdown These settings describe how the PMIC output rails are assigned to various system-level states. Also, the default trigger for each system-level state is described. All these settings can be changed though I2C after startup.2 FSM NVM Settings Register Name Field Name TPS65931211-Q1 Value Description RAIL_SEL_1 BUCK1_GRP_SEL 0x1 MCU rail group BUCK2_GRP_SEL 0x1 MCU rail group BUCK3_GRP_SEL 0x1 MCU rail group BUCK4_GRP_SEL 0x1 MCU rail group RAIL_SEL_2 BUCK5_GRP_SEL 0x1 MCU rail group LDO1_GRP_SEL 0x1 MCU rail group LDO2_GRP_SEL 0x3 OTHER rail group LDO3_GRP_SEL 0x1 MCU rail group RAIL_SEL_3 LDO4_GRP_SEL 0x1 MCU rail group VCCA_GRP_SEL 0x0 No group assigned FSM_TRIG_SEL_1 MCU_RAIL_TRIG 0x1 Orderly shutdown SOC_RAIL_TRIG 0x3 SOC power error OTHER_RAIL_TRIG 0x2 MCU power error SEVERE_ERR_TRIG 0x0 Immediate shutdown FSM_TRIG_SEL_2 MODERATE_ERR_TRIG 0x1 Orderly shutdown FSM NVM Settings Register Name Field Name TPS65931211-Q1 Value Description RAIL_SEL_1 BUCK1_GRP_SEL 0x1 MCU rail group BUCK2_GRP_SEL 0x1 MCU rail group BUCK3_GRP_SEL 0x1 MCU rail group BUCK4_GRP_SEL 0x1 MCU rail group RAIL_SEL_2 BUCK5_GRP_SEL 0x1 MCU rail group LDO1_GRP_SEL 0x1 MCU rail group LDO2_GRP_SEL 0x3 OTHER rail group LDO3_GRP_SEL 0x1 MCU rail group RAIL_SEL_3 LDO4_GRP_SEL 0x1 MCU rail group VCCA_GRP_SEL 0x0 No group assigned FSM_TRIG_SEL_1 MCU_RAIL_TRIG 0x1 Orderly shutdown SOC_RAIL_TRIG 0x3 SOC power error OTHER_RAIL_TRIG 0x2 MCU power error SEVERE_ERR_TRIG 0x0 Immediate shutdown FSM_TRIG_SEL_2 MODERATE_ERR_TRIG 0x1 Orderly shutdown Register Name Field Name TPS65931211-Q1 Value Description Register Name Field Name TPS65931211-Q1 Register NameField Name TPS65931211-Q1 TPS65931211-Q1 Value Description ValueDescription RAIL_SEL_1 BUCK1_GRP_SEL 0x1 MCU rail group BUCK2_GRP_SEL 0x1 MCU rail group BUCK3_GRP_SEL 0x1 MCU rail group BUCK4_GRP_SEL 0x1 MCU rail group RAIL_SEL_2 BUCK5_GRP_SEL 0x1 MCU rail group LDO1_GRP_SEL 0x1 MCU rail group LDO2_GRP_SEL 0x3 OTHER rail group LDO3_GRP_SEL 0x1 MCU rail group RAIL_SEL_3 LDO4_GRP_SEL 0x1 MCU rail group VCCA_GRP_SEL 0x0 No group assigned FSM_TRIG_SEL_1 MCU_RAIL_TRIG 0x1 Orderly shutdown SOC_RAIL_TRIG 0x3 SOC power error OTHER_RAIL_TRIG 0x2 MCU power error SEVERE_ERR_TRIG 0x0 Immediate shutdown FSM_TRIG_SEL_2 MODERATE_ERR_TRIG 0x1 Orderly shutdown RAIL_SEL_1 BUCK1_GRP_SEL 0x1 MCU rail group RAIL_SEL_1BUCK1_GRP_SEL 0x1 0x1 MCU rail group MCU rail group BUCK2_GRP_SEL 0x1 MCU rail group BUCK2_GRP_SEL 0x1 0x1 MCU rail group MCU rail group BUCK3_GRP_SEL 0x1 MCU rail group BUCK3_GRP_SEL 0x1 0x1 MCU rail group MCU rail group BUCK4_GRP_SEL 0x1 MCU rail group BUCK4_GRP_SEL 0x1 0x1 MCU rail group MCU rail group RAIL_SEL_2 BUCK5_GRP_SEL 0x1 MCU rail group RAIL_SEL_2BUCK5_GRP_SEL 0x1 0x1 MCU rail group MCU rail group LDO1_GRP_SEL 0x1 MCU rail group LDO1_GRP_SEL 0x1 0x1 MCU rail group MCU rail group LDO2_GRP_SEL 0x3 OTHER rail group LDO2_GRP_SEL 0x3 0x3 OTHER rail group OTHER rail group LDO3_GRP_SEL 0x1 MCU rail group LDO3_GRP_SEL 0x1 0x1 MCU rail group MCU rail group RAIL_SEL_3 LDO4_GRP_SEL 0x1 MCU rail group RAIL_SEL_3LDO4_GRP_SEL 0x1 0x1 MCU rail group MCU rail group VCCA_GRP_SEL 0x0 No group assigned VCCA_GRP_SEL 0x0 0x0 No group assigned No group assigned FSM_TRIG_SEL_1 MCU_RAIL_TRIG 0x1 Orderly shutdown FSM_TRIG_SEL_1MCU_RAIL_TRIG 0x1 0x1 Orderly shutdown Orderly shutdown SOC_RAIL_TRIG 0x3 SOC power error SOC_RAIL_TRIG 0x3 0x3 SOC power error SOC power error OTHER_RAIL_TRIG 0x2 MCU power error OTHER_RAIL_TRIG 0x2 0x2 MCU power error MCU power error SEVERE_ERR_TRIG 0x0 Immediate shutdown SEVERE_ERR_TRIG 0x0 0x0 Immediate shutdown Immediate shutdown FSM_TRIG_SEL_2 MODERATE_ERR_TRIG 0x1 Orderly shutdown FSM_TRIG_SEL_2MODERATE_ERR_TRIG 0x1 0x1 Orderly shutdown Orderly shutdown Interrupt Settings These settings detail the default configurations for what is monitored by nINT pin. All these settings can be changed through I2C after startup. Interrupt NVM Settings Register Name Field Name TPS65931211-Q1 Value Description FSM_TRIG_MASK_1 GPIO1_FSM_MASK 0x1 Masked GPIO1_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO2_FSM_MASK 0x1 Masked GPIO2_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO3_FSM_MASK 0x1 Masked GPIO3_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO4_FSM_MASK 0x1 Masked GPIO4_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' FSM_TRIG_MASK_2 GPIO5_FSM_MASK 0x0 Not masked GPIO5_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO6_FSM_MASK 0x0 Not masked GPIO6_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO7_FSM_MASK 0x1 Masked GPIO7_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO8_FSM_MASK 0x1 Masked GPIO8_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' FSM_TRIG_MASK_3 GPIO9_FSM_MASK 0x0 Not masked GPIO9_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO10_FSM_MASK 0x0 Not masked GPIO10_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO11_FSM_MASK 0x0 Not masked GPIO11_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' MASK_BUCK1_2 BUCK1_ILIM_MASK 0x0 Interrupt generated BUCK1_OV_MASK 0x0 Interrupt generated BUCK1_UV_MASK 0x0 Interrupt generated BUCK2_ILIM_MASK 0x0 Interrupt generated BUCK2_OV_MASK 0x0 Interrupt generated BUCK2_UV_MASK 0x0 Interrupt generated MASK_BUCK3_4 BUCK3_ILIM_MASK 0x0 Interrupt generated BUCK3_OV_MASK 0x0 Interrupt generated BUCK3_UV_MASK 0x0 Interrupt generated BUCK4_OV_MASK 0x0 Interrupt generated BUCK4_UV_MASK 0x0 Interrupt generated BUCK4_ILIM_MASK 0x0 Interrupt generated MASK_BUCK5 BUCK5_ILIM_MASK 0x0 Interrupt generated BUCK5_OV_MASK 0x0 Interrupt generated BUCK5_UV_MASK 0x0 Interrupt generated MASK_LDO1_2 LDO1_OV_MASK 0x0 Interrupt generated LDO1_UV_MASK 0x0 Interrupt generated LDO2_OV_MASK 0x0 Interrupt generated LDO2_UV_MASK 0x0 Interrupt generated LDO1_ILIM_MASK 0x0 Interrupt generated LDO2_ILIM_MASK 0x0 Interrupt generated MASK_LDO3_4 LDO3_OV_MASK 0x0 Interrupt generated LDO3_UV_MASK 0x0 Interrupt generated LDO4_OV_MASK 0x0 Interrupt generated LDO4_UV_MASK 0x0 Interrupt generated LDO3_ILIM_MASK 0x0 Interrupt generated LDO4_ILIM_MASK 0x0 Interrupt generated MASK_VMON VCCA_OV_MASK 0x0 Interrupt generated VCCA_UV_MASK 0x0 Interrupt generated MASK_GPIO1_8_FALL GPIO1_FALL_MASK 0x1 Interrupt not generated. GPIO2_FALL_MASK 0x1 Interrupt not generated. GPIO3_FALL_MASK 0x1 Interrupt not generated. GPIO4_FALL_MASK 0x1 Interrupt not generated. GPIO5_FALL_MASK 0x1 Interrupt not generated. GPIO6_FALL_MASK 0x1 Interrupt not generated. GPIO7_FALL_MASK 0x1 Interrupt not generated. GPIO8_FALL_MASK 0x1 Interrupt not generated. MASK_GPIO1_8_RISE GPIO1_RISE_MASK 0x1 Interrupt not generated. GPIO2_RISE_MASK 0x1 Interrupt not generated. GPIO3_RISE_MASK 0x1 Interrupt not generated. GPIO4_RISE_MASK 0x1 Interrupt not generated. GPIO5_RISE_MASK 0x1 Interrupt not generated. GPIO6_RISE_MASK 0x1 Interrupt not generated. GPIO7_RISE_MASK 0x1 Interrupt not generated. GPIO8_RISE_MASK 0x1 Interrupt not generated. MASK_GPIO9_11 / MASK_GPIO9_10 GPIO9_FALL_MASK 0x1 Interrupt not generated. GPIO9_RISE_MASK 0x1 Interrupt not generated. GPIO10_FALL_MASK 0x1 Interrupt not generated. GPIO11_FALL_MASK 0x1 Interrupt not generated. GPIO10_RISE_MASK 0x1 Interrupt not generated. GPIO11_RISE_MASK 0x1 Interrupt not generated. MASK_STARTUP NPWRON_START_MASK 0x1 Interrupt not generated. ENABLE_MASK 0x0 Interrupt generated FSD_MASK 0x1 Interrupt not generated. SOFT_REBOOT_MASK 0x0 Interrupt generated MASK_MISC TWARN_MASK 0x0 Interrupt generated BIST_PASS_MASK 0x0 Interrupt generated EXT_CLK_MASK 0x1 Interrupt not generated. MASK_MODERATE_ERR BIST_FAIL_MASK 0x0 Interrupt generated REG_CRC_ERR_MASK 0x0 Interrupt generated SPMI_ERR_MASK 0x1 Interrupt not generated. NPWRON_LONG_MASK 0x1 Interrupt not generated. NINT_READBACK_MASK 0x0 Interrupt generated NRSTOUT_READBACK_ MASK 0x0 Interrupt generated MASK_FSM_ERR IMM_SHUTDOWN_MASK 0x0 Interrupt generated MCU_PWR_ERR_MASK 0x0 Interrupt generated SOC_PWR_ERR_MASK 0x0 Interrupt generated ORD_SHUTDOWN_MASK 0x0 Interrupt generated MASK_COMM_ERR COMM_FRM_ERR_MASK 0x1 Interrupt not generated. COMM_CRC_ERR_MASK 0x0 Interrupt generated COMM_ADR_ERR_MASK 0x0 Interrupt generated I2C2_CRC_ERR_MASK 0x0 Interrupt generated I2C2_ADR_ERR_MASK 0x0 Interrupt generated MASK_READBACK_ERR EN_DRV_READBACK_ MASK 0x0 Interrupt generated NRSTOUT_SOC_ READBACK_MASK 0x1 Interrupt not generated. MASK_ESM ESM_SOC_PIN_MASK 0x1 Interrupt not generated. ESM_SOC_RST_MASK 0x1 Interrupt not generated. ESM_SOC_FAIL_MASK 0x1 Interrupt not generated. ESM_MCU_PIN_MASK 0x0 Interrupt generated ESM_MCU_RST_MASK 0x0 Interrupt generated ESM_MCU_FAIL_MASK 0x0 Interrupt generated GENERAL_REG_1 PFSM_ERR_MASK 0x0 Interrupt generated Interrupt Settings These settings detail the default configurations for what is monitored by nINT pin. All these settings can be changed through I2C after startup. Interrupt NVM Settings Register Name Field Name TPS65931211-Q1 Value Description FSM_TRIG_MASK_1 GPIO1_FSM_MASK 0x1 Masked GPIO1_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO2_FSM_MASK 0x1 Masked GPIO2_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO3_FSM_MASK 0x1 Masked GPIO3_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO4_FSM_MASK 0x1 Masked GPIO4_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' FSM_TRIG_MASK_2 GPIO5_FSM_MASK 0x0 Not masked GPIO5_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO6_FSM_MASK 0x0 Not masked GPIO6_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO7_FSM_MASK 0x1 Masked GPIO7_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO8_FSM_MASK 0x1 Masked GPIO8_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' FSM_TRIG_MASK_3 GPIO9_FSM_MASK 0x0 Not masked GPIO9_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO10_FSM_MASK 0x0 Not masked GPIO10_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO11_FSM_MASK 0x0 Not masked GPIO11_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' MASK_BUCK1_2 BUCK1_ILIM_MASK 0x0 Interrupt generated BUCK1_OV_MASK 0x0 Interrupt generated BUCK1_UV_MASK 0x0 Interrupt generated BUCK2_ILIM_MASK 0x0 Interrupt generated BUCK2_OV_MASK 0x0 Interrupt generated BUCK2_UV_MASK 0x0 Interrupt generated MASK_BUCK3_4 BUCK3_ILIM_MASK 0x0 Interrupt generated BUCK3_OV_MASK 0x0 Interrupt generated BUCK3_UV_MASK 0x0 Interrupt generated BUCK4_OV_MASK 0x0 Interrupt generated BUCK4_UV_MASK 0x0 Interrupt generated BUCK4_ILIM_MASK 0x0 Interrupt generated MASK_BUCK5 BUCK5_ILIM_MASK 0x0 Interrupt generated BUCK5_OV_MASK 0x0 Interrupt generated BUCK5_UV_MASK 0x0 Interrupt generated MASK_LDO1_2 LDO1_OV_MASK 0x0 Interrupt generated LDO1_UV_MASK 0x0 Interrupt generated LDO2_OV_MASK 0x0 Interrupt generated LDO2_UV_MASK 0x0 Interrupt generated LDO1_ILIM_MASK 0x0 Interrupt generated LDO2_ILIM_MASK 0x0 Interrupt generated MASK_LDO3_4 LDO3_OV_MASK 0x0 Interrupt generated LDO3_UV_MASK 0x0 Interrupt generated LDO4_OV_MASK 0x0 Interrupt generated LDO4_UV_MASK 0x0 Interrupt generated LDO3_ILIM_MASK 0x0 Interrupt generated LDO4_ILIM_MASK 0x0 Interrupt generated MASK_VMON VCCA_OV_MASK 0x0 Interrupt generated VCCA_UV_MASK 0x0 Interrupt generated MASK_GPIO1_8_FALL GPIO1_FALL_MASK 0x1 Interrupt not generated. GPIO2_FALL_MASK 0x1 Interrupt not generated. GPIO3_FALL_MASK 0x1 Interrupt not generated. GPIO4_FALL_MASK 0x1 Interrupt not generated. GPIO5_FALL_MASK 0x1 Interrupt not generated. GPIO6_FALL_MASK 0x1 Interrupt not generated. GPIO7_FALL_MASK 0x1 Interrupt not generated. GPIO8_FALL_MASK 0x1 Interrupt not generated. MASK_GPIO1_8_RISE GPIO1_RISE_MASK 0x1 Interrupt not generated. GPIO2_RISE_MASK 0x1 Interrupt not generated. GPIO3_RISE_MASK 0x1 Interrupt not generated. GPIO4_RISE_MASK 0x1 Interrupt not generated. GPIO5_RISE_MASK 0x1 Interrupt not generated. GPIO6_RISE_MASK 0x1 Interrupt not generated. GPIO7_RISE_MASK 0x1 Interrupt not generated. GPIO8_RISE_MASK 0x1 Interrupt not generated. MASK_GPIO9_11 / MASK_GPIO9_10 GPIO9_FALL_MASK 0x1 Interrupt not generated. GPIO9_RISE_MASK 0x1 Interrupt not generated. GPIO10_FALL_MASK 0x1 Interrupt not generated. GPIO11_FALL_MASK 0x1 Interrupt not generated. GPIO10_RISE_MASK 0x1 Interrupt not generated. GPIO11_RISE_MASK 0x1 Interrupt not generated. MASK_STARTUP NPWRON_START_MASK 0x1 Interrupt not generated. ENABLE_MASK 0x0 Interrupt generated FSD_MASK 0x1 Interrupt not generated. SOFT_REBOOT_MASK 0x0 Interrupt generated MASK_MISC TWARN_MASK 0x0 Interrupt generated BIST_PASS_MASK 0x0 Interrupt generated EXT_CLK_MASK 0x1 Interrupt not generated. MASK_MODERATE_ERR BIST_FAIL_MASK 0x0 Interrupt generated REG_CRC_ERR_MASK 0x0 Interrupt generated SPMI_ERR_MASK 0x1 Interrupt not generated. NPWRON_LONG_MASK 0x1 Interrupt not generated. NINT_READBACK_MASK 0x0 Interrupt generated NRSTOUT_READBACK_ MASK 0x0 Interrupt generated MASK_FSM_ERR IMM_SHUTDOWN_MASK 0x0 Interrupt generated MCU_PWR_ERR_MASK 0x0 Interrupt generated SOC_PWR_ERR_MASK 0x0 Interrupt generated ORD_SHUTDOWN_MASK 0x0 Interrupt generated MASK_COMM_ERR COMM_FRM_ERR_MASK 0x1 Interrupt not generated. COMM_CRC_ERR_MASK 0x0 Interrupt generated COMM_ADR_ERR_MASK 0x0 Interrupt generated I2C2_CRC_ERR_MASK 0x0 Interrupt generated I2C2_ADR_ERR_MASK 0x0 Interrupt generated MASK_READBACK_ERR EN_DRV_READBACK_ MASK 0x0 Interrupt generated NRSTOUT_SOC_ READBACK_MASK 0x1 Interrupt not generated. MASK_ESM ESM_SOC_PIN_MASK 0x1 Interrupt not generated. ESM_SOC_RST_MASK 0x1 Interrupt not generated. ESM_SOC_FAIL_MASK 0x1 Interrupt not generated. ESM_MCU_PIN_MASK 0x0 Interrupt generated ESM_MCU_RST_MASK 0x0 Interrupt generated ESM_MCU_FAIL_MASK 0x0 Interrupt generated GENERAL_REG_1 PFSM_ERR_MASK 0x0 Interrupt generated These settings detail the default configurations for what is monitored by nINT pin. All these settings can be changed through I2C after startup. Interrupt NVM Settings Register Name Field Name TPS65931211-Q1 Value Description FSM_TRIG_MASK_1 GPIO1_FSM_MASK 0x1 Masked GPIO1_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO2_FSM_MASK 0x1 Masked GPIO2_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO3_FSM_MASK 0x1 Masked GPIO3_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO4_FSM_MASK 0x1 Masked GPIO4_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' FSM_TRIG_MASK_2 GPIO5_FSM_MASK 0x0 Not masked GPIO5_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO6_FSM_MASK 0x0 Not masked GPIO6_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO7_FSM_MASK 0x1 Masked GPIO7_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO8_FSM_MASK 0x1 Masked GPIO8_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' FSM_TRIG_MASK_3 GPIO9_FSM_MASK 0x0 Not masked GPIO9_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO10_FSM_MASK 0x0 Not masked GPIO10_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO11_FSM_MASK 0x0 Not masked GPIO11_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' MASK_BUCK1_2 BUCK1_ILIM_MASK 0x0 Interrupt generated BUCK1_OV_MASK 0x0 Interrupt generated BUCK1_UV_MASK 0x0 Interrupt generated BUCK2_ILIM_MASK 0x0 Interrupt generated BUCK2_OV_MASK 0x0 Interrupt generated BUCK2_UV_MASK 0x0 Interrupt generated MASK_BUCK3_4 BUCK3_ILIM_MASK 0x0 Interrupt generated BUCK3_OV_MASK 0x0 Interrupt generated BUCK3_UV_MASK 0x0 Interrupt generated BUCK4_OV_MASK 0x0 Interrupt generated BUCK4_UV_MASK 0x0 Interrupt generated BUCK4_ILIM_MASK 0x0 Interrupt generated MASK_BUCK5 BUCK5_ILIM_MASK 0x0 Interrupt generated BUCK5_OV_MASK 0x0 Interrupt generated BUCK5_UV_MASK 0x0 Interrupt generated MASK_LDO1_2 LDO1_OV_MASK 0x0 Interrupt generated LDO1_UV_MASK 0x0 Interrupt generated LDO2_OV_MASK 0x0 Interrupt generated LDO2_UV_MASK 0x0 Interrupt generated LDO1_ILIM_MASK 0x0 Interrupt generated LDO2_ILIM_MASK 0x0 Interrupt generated MASK_LDO3_4 LDO3_OV_MASK 0x0 Interrupt generated LDO3_UV_MASK 0x0 Interrupt generated LDO4_OV_MASK 0x0 Interrupt generated LDO4_UV_MASK 0x0 Interrupt generated LDO3_ILIM_MASK 0x0 Interrupt generated LDO4_ILIM_MASK 0x0 Interrupt generated MASK_VMON VCCA_OV_MASK 0x0 Interrupt generated VCCA_UV_MASK 0x0 Interrupt generated MASK_GPIO1_8_FALL GPIO1_FALL_MASK 0x1 Interrupt not generated. GPIO2_FALL_MASK 0x1 Interrupt not generated. GPIO3_FALL_MASK 0x1 Interrupt not generated. GPIO4_FALL_MASK 0x1 Interrupt not generated. GPIO5_FALL_MASK 0x1 Interrupt not generated. GPIO6_FALL_MASK 0x1 Interrupt not generated. GPIO7_FALL_MASK 0x1 Interrupt not generated. GPIO8_FALL_MASK 0x1 Interrupt not generated. MASK_GPIO1_8_RISE GPIO1_RISE_MASK 0x1 Interrupt not generated. GPIO2_RISE_MASK 0x1 Interrupt not generated. GPIO3_RISE_MASK 0x1 Interrupt not generated. GPIO4_RISE_MASK 0x1 Interrupt not generated. GPIO5_RISE_MASK 0x1 Interrupt not generated. GPIO6_RISE_MASK 0x1 Interrupt not generated. GPIO7_RISE_MASK 0x1 Interrupt not generated. GPIO8_RISE_MASK 0x1 Interrupt not generated. MASK_GPIO9_11 / MASK_GPIO9_10 GPIO9_FALL_MASK 0x1 Interrupt not generated. GPIO9_RISE_MASK 0x1 Interrupt not generated. GPIO10_FALL_MASK 0x1 Interrupt not generated. GPIO11_FALL_MASK 0x1 Interrupt not generated. GPIO10_RISE_MASK 0x1 Interrupt not generated. GPIO11_RISE_MASK 0x1 Interrupt not generated. MASK_STARTUP NPWRON_START_MASK 0x1 Interrupt not generated. ENABLE_MASK 0x0 Interrupt generated FSD_MASK 0x1 Interrupt not generated. SOFT_REBOOT_MASK 0x0 Interrupt generated MASK_MISC TWARN_MASK 0x0 Interrupt generated BIST_PASS_MASK 0x0 Interrupt generated EXT_CLK_MASK 0x1 Interrupt not generated. MASK_MODERATE_ERR BIST_FAIL_MASK 0x0 Interrupt generated REG_CRC_ERR_MASK 0x0 Interrupt generated SPMI_ERR_MASK 0x1 Interrupt not generated. NPWRON_LONG_MASK 0x1 Interrupt not generated. NINT_READBACK_MASK 0x0 Interrupt generated NRSTOUT_READBACK_ MASK 0x0 Interrupt generated MASK_FSM_ERR IMM_SHUTDOWN_MASK 0x0 Interrupt generated MCU_PWR_ERR_MASK 0x0 Interrupt generated SOC_PWR_ERR_MASK 0x0 Interrupt generated ORD_SHUTDOWN_MASK 0x0 Interrupt generated MASK_COMM_ERR COMM_FRM_ERR_MASK 0x1 Interrupt not generated. COMM_CRC_ERR_MASK 0x0 Interrupt generated COMM_ADR_ERR_MASK 0x0 Interrupt generated I2C2_CRC_ERR_MASK 0x0 Interrupt generated I2C2_ADR_ERR_MASK 0x0 Interrupt generated MASK_READBACK_ERR EN_DRV_READBACK_ MASK 0x0 Interrupt generated NRSTOUT_SOC_ READBACK_MASK 0x1 Interrupt not generated. MASK_ESM ESM_SOC_PIN_MASK 0x1 Interrupt not generated. ESM_SOC_RST_MASK 0x1 Interrupt not generated. ESM_SOC_FAIL_MASK 0x1 Interrupt not generated. ESM_MCU_PIN_MASK 0x0 Interrupt generated ESM_MCU_RST_MASK 0x0 Interrupt generated ESM_MCU_FAIL_MASK 0x0 Interrupt generated GENERAL_REG_1 PFSM_ERR_MASK 0x0 Interrupt generated These settings detail the default configurations for what is monitored by nINT pin. All these settings can be changed through I2C after startup.2 Interrupt NVM Settings Register Name Field Name TPS65931211-Q1 Value Description FSM_TRIG_MASK_1 GPIO1_FSM_MASK 0x1 Masked GPIO1_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO2_FSM_MASK 0x1 Masked GPIO2_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO3_FSM_MASK 0x1 Masked GPIO3_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO4_FSM_MASK 0x1 Masked GPIO4_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' FSM_TRIG_MASK_2 GPIO5_FSM_MASK 0x0 Not masked GPIO5_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO6_FSM_MASK 0x0 Not masked GPIO6_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO7_FSM_MASK 0x1 Masked GPIO7_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO8_FSM_MASK 0x1 Masked GPIO8_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' FSM_TRIG_MASK_3 GPIO9_FSM_MASK 0x0 Not masked GPIO9_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO10_FSM_MASK 0x0 Not masked GPIO10_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO11_FSM_MASK 0x0 Not masked GPIO11_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' MASK_BUCK1_2 BUCK1_ILIM_MASK 0x0 Interrupt generated BUCK1_OV_MASK 0x0 Interrupt generated BUCK1_UV_MASK 0x0 Interrupt generated BUCK2_ILIM_MASK 0x0 Interrupt generated BUCK2_OV_MASK 0x0 Interrupt generated BUCK2_UV_MASK 0x0 Interrupt generated MASK_BUCK3_4 BUCK3_ILIM_MASK 0x0 Interrupt generated BUCK3_OV_MASK 0x0 Interrupt generated BUCK3_UV_MASK 0x0 Interrupt generated BUCK4_OV_MASK 0x0 Interrupt generated BUCK4_UV_MASK 0x0 Interrupt generated BUCK4_ILIM_MASK 0x0 Interrupt generated MASK_BUCK5 BUCK5_ILIM_MASK 0x0 Interrupt generated BUCK5_OV_MASK 0x0 Interrupt generated BUCK5_UV_MASK 0x0 Interrupt generated MASK_LDO1_2 LDO1_OV_MASK 0x0 Interrupt generated LDO1_UV_MASK 0x0 Interrupt generated LDO2_OV_MASK 0x0 Interrupt generated LDO2_UV_MASK 0x0 Interrupt generated LDO1_ILIM_MASK 0x0 Interrupt generated LDO2_ILIM_MASK 0x0 Interrupt generated MASK_LDO3_4 LDO3_OV_MASK 0x0 Interrupt generated LDO3_UV_MASK 0x0 Interrupt generated LDO4_OV_MASK 0x0 Interrupt generated LDO4_UV_MASK 0x0 Interrupt generated LDO3_ILIM_MASK 0x0 Interrupt generated LDO4_ILIM_MASK 0x0 Interrupt generated MASK_VMON VCCA_OV_MASK 0x0 Interrupt generated VCCA_UV_MASK 0x0 Interrupt generated MASK_GPIO1_8_FALL GPIO1_FALL_MASK 0x1 Interrupt not generated. GPIO2_FALL_MASK 0x1 Interrupt not generated. GPIO3_FALL_MASK 0x1 Interrupt not generated. GPIO4_FALL_MASK 0x1 Interrupt not generated. GPIO5_FALL_MASK 0x1 Interrupt not generated. GPIO6_FALL_MASK 0x1 Interrupt not generated. GPIO7_FALL_MASK 0x1 Interrupt not generated. GPIO8_FALL_MASK 0x1 Interrupt not generated. MASK_GPIO1_8_RISE GPIO1_RISE_MASK 0x1 Interrupt not generated. GPIO2_RISE_MASK 0x1 Interrupt not generated. GPIO3_RISE_MASK 0x1 Interrupt not generated. GPIO4_RISE_MASK 0x1 Interrupt not generated. GPIO5_RISE_MASK 0x1 Interrupt not generated. GPIO6_RISE_MASK 0x1 Interrupt not generated. GPIO7_RISE_MASK 0x1 Interrupt not generated. GPIO8_RISE_MASK 0x1 Interrupt not generated. MASK_GPIO9_11 / MASK_GPIO9_10 GPIO9_FALL_MASK 0x1 Interrupt not generated. GPIO9_RISE_MASK 0x1 Interrupt not generated. GPIO10_FALL_MASK 0x1 Interrupt not generated. GPIO11_FALL_MASK 0x1 Interrupt not generated. GPIO10_RISE_MASK 0x1 Interrupt not generated. GPIO11_RISE_MASK 0x1 Interrupt not generated. MASK_STARTUP NPWRON_START_MASK 0x1 Interrupt not generated. ENABLE_MASK 0x0 Interrupt generated FSD_MASK 0x1 Interrupt not generated. SOFT_REBOOT_MASK 0x0 Interrupt generated MASK_MISC TWARN_MASK 0x0 Interrupt generated BIST_PASS_MASK 0x0 Interrupt generated EXT_CLK_MASK 0x1 Interrupt not generated. MASK_MODERATE_ERR BIST_FAIL_MASK 0x0 Interrupt generated REG_CRC_ERR_MASK 0x0 Interrupt generated SPMI_ERR_MASK 0x1 Interrupt not generated. NPWRON_LONG_MASK 0x1 Interrupt not generated. NINT_READBACK_MASK 0x0 Interrupt generated NRSTOUT_READBACK_ MASK 0x0 Interrupt generated MASK_FSM_ERR IMM_SHUTDOWN_MASK 0x0 Interrupt generated MCU_PWR_ERR_MASK 0x0 Interrupt generated SOC_PWR_ERR_MASK 0x0 Interrupt generated ORD_SHUTDOWN_MASK 0x0 Interrupt generated MASK_COMM_ERR COMM_FRM_ERR_MASK 0x1 Interrupt not generated. COMM_CRC_ERR_MASK 0x0 Interrupt generated COMM_ADR_ERR_MASK 0x0 Interrupt generated I2C2_CRC_ERR_MASK 0x0 Interrupt generated I2C2_ADR_ERR_MASK 0x0 Interrupt generated MASK_READBACK_ERR EN_DRV_READBACK_ MASK 0x0 Interrupt generated NRSTOUT_SOC_ READBACK_MASK 0x1 Interrupt not generated. MASK_ESM ESM_SOC_PIN_MASK 0x1 Interrupt not generated. ESM_SOC_RST_MASK 0x1 Interrupt not generated. ESM_SOC_FAIL_MASK 0x1 Interrupt not generated. ESM_MCU_PIN_MASK 0x0 Interrupt generated ESM_MCU_RST_MASK 0x0 Interrupt generated ESM_MCU_FAIL_MASK 0x0 Interrupt generated GENERAL_REG_1 PFSM_ERR_MASK 0x0 Interrupt generated Interrupt NVM Settings Register Name Field Name TPS65931211-Q1 Value Description FSM_TRIG_MASK_1 GPIO1_FSM_MASK 0x1 Masked GPIO1_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO2_FSM_MASK 0x1 Masked GPIO2_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO3_FSM_MASK 0x1 Masked GPIO3_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO4_FSM_MASK 0x1 Masked GPIO4_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' FSM_TRIG_MASK_2 GPIO5_FSM_MASK 0x0 Not masked GPIO5_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO6_FSM_MASK 0x0 Not masked GPIO6_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO7_FSM_MASK 0x1 Masked GPIO7_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO8_FSM_MASK 0x1 Masked GPIO8_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' FSM_TRIG_MASK_3 GPIO9_FSM_MASK 0x0 Not masked GPIO9_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO10_FSM_MASK 0x0 Not masked GPIO10_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO11_FSM_MASK 0x0 Not masked GPIO11_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' MASK_BUCK1_2 BUCK1_ILIM_MASK 0x0 Interrupt generated BUCK1_OV_MASK 0x0 Interrupt generated BUCK1_UV_MASK 0x0 Interrupt generated BUCK2_ILIM_MASK 0x0 Interrupt generated BUCK2_OV_MASK 0x0 Interrupt generated BUCK2_UV_MASK 0x0 Interrupt generated MASK_BUCK3_4 BUCK3_ILIM_MASK 0x0 Interrupt generated BUCK3_OV_MASK 0x0 Interrupt generated BUCK3_UV_MASK 0x0 Interrupt generated BUCK4_OV_MASK 0x0 Interrupt generated BUCK4_UV_MASK 0x0 Interrupt generated BUCK4_ILIM_MASK 0x0 Interrupt generated MASK_BUCK5 BUCK5_ILIM_MASK 0x0 Interrupt generated BUCK5_OV_MASK 0x0 Interrupt generated BUCK5_UV_MASK 0x0 Interrupt generated MASK_LDO1_2 LDO1_OV_MASK 0x0 Interrupt generated LDO1_UV_MASK 0x0 Interrupt generated LDO2_OV_MASK 0x0 Interrupt generated LDO2_UV_MASK 0x0 Interrupt generated LDO1_ILIM_MASK 0x0 Interrupt generated LDO2_ILIM_MASK 0x0 Interrupt generated MASK_LDO3_4 LDO3_OV_MASK 0x0 Interrupt generated LDO3_UV_MASK 0x0 Interrupt generated LDO4_OV_MASK 0x0 Interrupt generated LDO4_UV_MASK 0x0 Interrupt generated LDO3_ILIM_MASK 0x0 Interrupt generated LDO4_ILIM_MASK 0x0 Interrupt generated MASK_VMON VCCA_OV_MASK 0x0 Interrupt generated VCCA_UV_MASK 0x0 Interrupt generated MASK_GPIO1_8_FALL GPIO1_FALL_MASK 0x1 Interrupt not generated. GPIO2_FALL_MASK 0x1 Interrupt not generated. GPIO3_FALL_MASK 0x1 Interrupt not generated. GPIO4_FALL_MASK 0x1 Interrupt not generated. GPIO5_FALL_MASK 0x1 Interrupt not generated. GPIO6_FALL_MASK 0x1 Interrupt not generated. GPIO7_FALL_MASK 0x1 Interrupt not generated. GPIO8_FALL_MASK 0x1 Interrupt not generated. MASK_GPIO1_8_RISE GPIO1_RISE_MASK 0x1 Interrupt not generated. GPIO2_RISE_MASK 0x1 Interrupt not generated. GPIO3_RISE_MASK 0x1 Interrupt not generated. GPIO4_RISE_MASK 0x1 Interrupt not generated. GPIO5_RISE_MASK 0x1 Interrupt not generated. GPIO6_RISE_MASK 0x1 Interrupt not generated. GPIO7_RISE_MASK 0x1 Interrupt not generated. GPIO8_RISE_MASK 0x1 Interrupt not generated. MASK_GPIO9_11 / MASK_GPIO9_10 GPIO9_FALL_MASK 0x1 Interrupt not generated. GPIO9_RISE_MASK 0x1 Interrupt not generated. GPIO10_FALL_MASK 0x1 Interrupt not generated. GPIO11_FALL_MASK 0x1 Interrupt not generated. GPIO10_RISE_MASK 0x1 Interrupt not generated. GPIO11_RISE_MASK 0x1 Interrupt not generated. MASK_STARTUP NPWRON_START_MASK 0x1 Interrupt not generated. ENABLE_MASK 0x0 Interrupt generated FSD_MASK 0x1 Interrupt not generated. SOFT_REBOOT_MASK 0x0 Interrupt generated MASK_MISC TWARN_MASK 0x0 Interrupt generated BIST_PASS_MASK 0x0 Interrupt generated EXT_CLK_MASK 0x1 Interrupt not generated. MASK_MODERATE_ERR BIST_FAIL_MASK 0x0 Interrupt generated REG_CRC_ERR_MASK 0x0 Interrupt generated SPMI_ERR_MASK 0x1 Interrupt not generated. NPWRON_LONG_MASK 0x1 Interrupt not generated. NINT_READBACK_MASK 0x0 Interrupt generated NRSTOUT_READBACK_ MASK 0x0 Interrupt generated MASK_FSM_ERR IMM_SHUTDOWN_MASK 0x0 Interrupt generated MCU_PWR_ERR_MASK 0x0 Interrupt generated SOC_PWR_ERR_MASK 0x0 Interrupt generated ORD_SHUTDOWN_MASK 0x0 Interrupt generated MASK_COMM_ERR COMM_FRM_ERR_MASK 0x1 Interrupt not generated. COMM_CRC_ERR_MASK 0x0 Interrupt generated COMM_ADR_ERR_MASK 0x0 Interrupt generated I2C2_CRC_ERR_MASK 0x0 Interrupt generated I2C2_ADR_ERR_MASK 0x0 Interrupt generated MASK_READBACK_ERR EN_DRV_READBACK_ MASK 0x0 Interrupt generated NRSTOUT_SOC_ READBACK_MASK 0x1 Interrupt not generated. MASK_ESM ESM_SOC_PIN_MASK 0x1 Interrupt not generated. ESM_SOC_RST_MASK 0x1 Interrupt not generated. ESM_SOC_FAIL_MASK 0x1 Interrupt not generated. ESM_MCU_PIN_MASK 0x0 Interrupt generated ESM_MCU_RST_MASK 0x0 Interrupt generated ESM_MCU_FAIL_MASK 0x0 Interrupt generated GENERAL_REG_1 PFSM_ERR_MASK 0x0 Interrupt generated Register Name Field Name TPS65931211-Q1 Value Description Register Name Field Name TPS65931211-Q1 Register NameField Name TPS65931211-Q1 TPS65931211-Q1 Value Description ValueDescription FSM_TRIG_MASK_1 GPIO1_FSM_MASK 0x1 Masked GPIO1_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO2_FSM_MASK 0x1 Masked GPIO2_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO3_FSM_MASK 0x1 Masked GPIO3_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO4_FSM_MASK 0x1 Masked GPIO4_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' FSM_TRIG_MASK_2 GPIO5_FSM_MASK 0x0 Not masked GPIO5_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO6_FSM_MASK 0x0 Not masked GPIO6_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO7_FSM_MASK 0x1 Masked GPIO7_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO8_FSM_MASK 0x1 Masked GPIO8_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' FSM_TRIG_MASK_3 GPIO9_FSM_MASK 0x0 Not masked GPIO9_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO10_FSM_MASK 0x0 Not masked GPIO10_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO11_FSM_MASK 0x0 Not masked GPIO11_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' MASK_BUCK1_2 BUCK1_ILIM_MASK 0x0 Interrupt generated BUCK1_OV_MASK 0x0 Interrupt generated BUCK1_UV_MASK 0x0 Interrupt generated BUCK2_ILIM_MASK 0x0 Interrupt generated BUCK2_OV_MASK 0x0 Interrupt generated BUCK2_UV_MASK 0x0 Interrupt generated MASK_BUCK3_4 BUCK3_ILIM_MASK 0x0 Interrupt generated BUCK3_OV_MASK 0x0 Interrupt generated BUCK3_UV_MASK 0x0 Interrupt generated BUCK4_OV_MASK 0x0 Interrupt generated BUCK4_UV_MASK 0x0 Interrupt generated BUCK4_ILIM_MASK 0x0 Interrupt generated MASK_BUCK5 BUCK5_ILIM_MASK 0x0 Interrupt generated BUCK5_OV_MASK 0x0 Interrupt generated BUCK5_UV_MASK 0x0 Interrupt generated MASK_LDO1_2 LDO1_OV_MASK 0x0 Interrupt generated LDO1_UV_MASK 0x0 Interrupt generated LDO2_OV_MASK 0x0 Interrupt generated LDO2_UV_MASK 0x0 Interrupt generated LDO1_ILIM_MASK 0x0 Interrupt generated LDO2_ILIM_MASK 0x0 Interrupt generated MASK_LDO3_4 LDO3_OV_MASK 0x0 Interrupt generated LDO3_UV_MASK 0x0 Interrupt generated LDO4_OV_MASK 0x0 Interrupt generated LDO4_UV_MASK 0x0 Interrupt generated LDO3_ILIM_MASK 0x0 Interrupt generated LDO4_ILIM_MASK 0x0 Interrupt generated MASK_VMON VCCA_OV_MASK 0x0 Interrupt generated VCCA_UV_MASK 0x0 Interrupt generated MASK_GPIO1_8_FALL GPIO1_FALL_MASK 0x1 Interrupt not generated. GPIO2_FALL_MASK 0x1 Interrupt not generated. GPIO3_FALL_MASK 0x1 Interrupt not generated. GPIO4_FALL_MASK 0x1 Interrupt not generated. GPIO5_FALL_MASK 0x1 Interrupt not generated. GPIO6_FALL_MASK 0x1 Interrupt not generated. GPIO7_FALL_MASK 0x1 Interrupt not generated. GPIO8_FALL_MASK 0x1 Interrupt not generated. MASK_GPIO1_8_RISE GPIO1_RISE_MASK 0x1 Interrupt not generated. GPIO2_RISE_MASK 0x1 Interrupt not generated. GPIO3_RISE_MASK 0x1 Interrupt not generated. GPIO4_RISE_MASK 0x1 Interrupt not generated. GPIO5_RISE_MASK 0x1 Interrupt not generated. GPIO6_RISE_MASK 0x1 Interrupt not generated. GPIO7_RISE_MASK 0x1 Interrupt not generated. GPIO8_RISE_MASK 0x1 Interrupt not generated. MASK_GPIO9_11 / MASK_GPIO9_10 GPIO9_FALL_MASK 0x1 Interrupt not generated. GPIO9_RISE_MASK 0x1 Interrupt not generated. GPIO10_FALL_MASK 0x1 Interrupt not generated. GPIO11_FALL_MASK 0x1 Interrupt not generated. GPIO10_RISE_MASK 0x1 Interrupt not generated. GPIO11_RISE_MASK 0x1 Interrupt not generated. MASK_STARTUP NPWRON_START_MASK 0x1 Interrupt not generated. ENABLE_MASK 0x0 Interrupt generated FSD_MASK 0x1 Interrupt not generated. SOFT_REBOOT_MASK 0x0 Interrupt generated MASK_MISC TWARN_MASK 0x0 Interrupt generated BIST_PASS_MASK 0x0 Interrupt generated EXT_CLK_MASK 0x1 Interrupt not generated. MASK_MODERATE_ERR BIST_FAIL_MASK 0x0 Interrupt generated REG_CRC_ERR_MASK 0x0 Interrupt generated SPMI_ERR_MASK 0x1 Interrupt not generated. NPWRON_LONG_MASK 0x1 Interrupt not generated. NINT_READBACK_MASK 0x0 Interrupt generated NRSTOUT_READBACK_ MASK 0x0 Interrupt generated MASK_FSM_ERR IMM_SHUTDOWN_MASK 0x0 Interrupt generated MCU_PWR_ERR_MASK 0x0 Interrupt generated SOC_PWR_ERR_MASK 0x0 Interrupt generated ORD_SHUTDOWN_MASK 0x0 Interrupt generated MASK_COMM_ERR COMM_FRM_ERR_MASK 0x1 Interrupt not generated. COMM_CRC_ERR_MASK 0x0 Interrupt generated COMM_ADR_ERR_MASK 0x0 Interrupt generated I2C2_CRC_ERR_MASK 0x0 Interrupt generated I2C2_ADR_ERR_MASK 0x0 Interrupt generated MASK_READBACK_ERR EN_DRV_READBACK_ MASK 0x0 Interrupt generated NRSTOUT_SOC_ READBACK_MASK 0x1 Interrupt not generated. MASK_ESM ESM_SOC_PIN_MASK 0x1 Interrupt not generated. ESM_SOC_RST_MASK 0x1 Interrupt not generated. ESM_SOC_FAIL_MASK 0x1 Interrupt not generated. ESM_MCU_PIN_MASK 0x0 Interrupt generated ESM_MCU_RST_MASK 0x0 Interrupt generated ESM_MCU_FAIL_MASK 0x0 Interrupt generated GENERAL_REG_1 PFSM_ERR_MASK 0x0 Interrupt generated FSM_TRIG_MASK_1 GPIO1_FSM_MASK 0x1 Masked FSM_TRIG_MASK_1GPIO1_FSM_MASK 0x1 0x1 Masked Masked GPIO1_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO1_FSM_MASK_POL 0x0 0x0 Low; Masking sets signal value to '0' Low; Masking sets signal value to '0' GPIO2_FSM_MASK 0x1 Masked GPIO2_FSM_MASK 0x1 0x1 Masked Masked GPIO2_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO2_FSM_MASK_POL 0x0 0x0 Low; Masking sets signal value to '0' Low; Masking sets signal value to '0' GPIO3_FSM_MASK 0x1 Masked GPIO3_FSM_MASK 0x1 0x1 Masked Masked GPIO3_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO3_FSM_MASK_POL 0x0 0x0 Low; Masking sets signal value to '0' Low; Masking sets signal value to '0' GPIO4_FSM_MASK 0x1 Masked GPIO4_FSM_MASK 0x1 0x1 Masked Masked GPIO4_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO4_FSM_MASK_POL 0x0 0x0 Low; Masking sets signal value to '0' Low; Masking sets signal value to '0' FSM_TRIG_MASK_2 GPIO5_FSM_MASK 0x0 Not masked FSM_TRIG_MASK_2GPIO5_FSM_MASK 0x0 0x0 Not masked Not masked GPIO5_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO5_FSM_MASK_POL 0x0 0x0 Low; Masking sets signal value to '0' Low; Masking sets signal value to '0' GPIO6_FSM_MASK 0x0 Not masked GPIO6_FSM_MASK 0x0 0x0 Not masked Not masked GPIO6_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO6_FSM_MASK_POL 0x0 0x0 Low; Masking sets signal value to '0' Low; Masking sets signal value to '0' GPIO7_FSM_MASK 0x1 Masked GPIO7_FSM_MASK 0x1 0x1 Masked Masked GPIO7_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO7_FSM_MASK_POL 0x0 0x0 Low; Masking sets signal value to '0' Low; Masking sets signal value to '0' GPIO8_FSM_MASK 0x1 Masked GPIO8_FSM_MASK 0x1 0x1 Masked Masked GPIO8_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO8_FSM_MASK_POL 0x0 0x0 Low; Masking sets signal value to '0' Low; Masking sets signal value to '0' FSM_TRIG_MASK_3 GPIO9_FSM_MASK 0x0 Not masked FSM_TRIG_MASK_3GPIO9_FSM_MASK 0x0 0x0 Not masked Not masked GPIO9_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO9_FSM_MASK_POL 0x0 0x0 Low; Masking sets signal value to '0' Low; Masking sets signal value to '0' GPIO10_FSM_MASK 0x0 Not masked GPIO10_FSM_MASK 0x0 0x0 Not masked Not masked GPIO10_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO10_FSM_MASK_POL 0x0 0x0 Low; Masking sets signal value to '0' Low; Masking sets signal value to '0' GPIO11_FSM_MASK 0x0 Not masked GPIO11_FSM_MASK 0x0 0x0 Not masked Not masked GPIO11_FSM_MASK_POL 0x0 Low; Masking sets signal value to '0' GPIO11_FSM_MASK_POL 0x0 0x0 Low; Masking sets signal value to '0' Low; Masking sets signal value to '0' MASK_BUCK1_2 BUCK1_ILIM_MASK 0x0 Interrupt generated MASK_BUCK1_2BUCK1_ILIM_MASK 0x0 0x0 Interrupt generated Interrupt generated BUCK1_OV_MASK 0x0 Interrupt generated BUCK1_OV_MASK 0x0 0x0 Interrupt generated Interrupt generated BUCK1_UV_MASK 0x0 Interrupt generated BUCK1_UV_MASK 0x0 0x0 Interrupt generated Interrupt generated BUCK2_ILIM_MASK 0x0 Interrupt generated BUCK2_ILIM_MASK 0x0 0x0 Interrupt generated Interrupt generated BUCK2_OV_MASK 0x0 Interrupt generated BUCK2_OV_MASK 0x0 0x0 Interrupt generated Interrupt generated BUCK2_UV_MASK 0x0 Interrupt generated BUCK2_UV_MASK 0x0 0x0 Interrupt generated Interrupt generated MASK_BUCK3_4 BUCK3_ILIM_MASK 0x0 Interrupt generated MASK_BUCK3_4BUCK3_ILIM_MASK 0x0 0x0 Interrupt generated Interrupt generated BUCK3_OV_MASK 0x0 Interrupt generated BUCK3_OV_MASK 0x0 0x0 Interrupt generated Interrupt generated BUCK3_UV_MASK 0x0 Interrupt generated BUCK3_UV_MASK 0x0 0x0 Interrupt generated Interrupt generated BUCK4_OV_MASK 0x0 Interrupt generated BUCK4_OV_MASK 0x0 0x0 Interrupt generated Interrupt generated BUCK4_UV_MASK 0x0 Interrupt generated BUCK4_UV_MASK 0x0 0x0 Interrupt generated Interrupt generated BUCK4_ILIM_MASK 0x0 Interrupt generated BUCK4_ILIM_MASK 0x0 0x0 Interrupt generated Interrupt generated MASK_BUCK5 BUCK5_ILIM_MASK 0x0 Interrupt generated MASK_BUCK5BUCK5_ILIM_MASK 0x0 0x0 Interrupt generated Interrupt generated BUCK5_OV_MASK 0x0 Interrupt generated BUCK5_OV_MASK 0x0 0x0 Interrupt generated Interrupt generated BUCK5_UV_MASK 0x0 Interrupt generated BUCK5_UV_MASK 0x0 0x0 Interrupt generated Interrupt generated MASK_LDO1_2 LDO1_OV_MASK 0x0 Interrupt generated MASK_LDO1_2LDO1_OV_MASK 0x0 0x0 Interrupt generated Interrupt generated LDO1_UV_MASK 0x0 Interrupt generated LDO1_UV_MASK 0x0 0x0 Interrupt generated Interrupt generated LDO2_OV_MASK 0x0 Interrupt generated LDO2_OV_MASK 0x0 0x0 Interrupt generated Interrupt generated LDO2_UV_MASK 0x0 Interrupt generated LDO2_UV_MASK 0x0 0x0 Interrupt generated Interrupt generated LDO1_ILIM_MASK 0x0 Interrupt generated LDO1_ILIM_MASK 0x0 0x0 Interrupt generated Interrupt generated LDO2_ILIM_MASK 0x0 Interrupt generated LDO2_ILIM_MASK 0x0 0x0 Interrupt generated Interrupt generated MASK_LDO3_4 LDO3_OV_MASK 0x0 Interrupt generated MASK_LDO3_4LDO3_OV_MASK 0x0 0x0 Interrupt generated Interrupt generated LDO3_UV_MASK 0x0 Interrupt generated LDO3_UV_MASK 0x0 0x0 Interrupt generated Interrupt generated LDO4_OV_MASK 0x0 Interrupt generated LDO4_OV_MASK 0x0 0x0 Interrupt generated Interrupt generated LDO4_UV_MASK 0x0 Interrupt generated LDO4_UV_MASK 0x0 0x0 Interrupt generated Interrupt generated LDO3_ILIM_MASK 0x0 Interrupt generated LDO3_ILIM_MASK 0x0 0x0 Interrupt generated Interrupt generated LDO4_ILIM_MASK 0x0 Interrupt generated LDO4_ILIM_MASK 0x0 0x0 Interrupt generated Interrupt generated MASK_VMON VCCA_OV_MASK 0x0 Interrupt generated MASK_VMONVCCA_OV_MASK 0x0 0x0 Interrupt generated Interrupt generated VCCA_UV_MASK 0x0 Interrupt generated VCCA_UV_MASK 0x0 0x0 Interrupt generated Interrupt generated MASK_GPIO1_8_FALL GPIO1_FALL_MASK 0x1 Interrupt not generated. MASK_GPIO1_8_FALLGPIO1_FALL_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. GPIO2_FALL_MASK 0x1 Interrupt not generated. GPIO2_FALL_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. GPIO3_FALL_MASK 0x1 Interrupt not generated. GPIO3_FALL_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. GPIO4_FALL_MASK 0x1 Interrupt not generated. GPIO4_FALL_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. GPIO5_FALL_MASK 0x1 Interrupt not generated. GPIO5_FALL_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. GPIO6_FALL_MASK 0x1 Interrupt not generated. GPIO6_FALL_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. GPIO7_FALL_MASK 0x1 Interrupt not generated. GPIO7_FALL_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. GPIO8_FALL_MASK 0x1 Interrupt not generated. GPIO8_FALL_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. MASK_GPIO1_8_RISE GPIO1_RISE_MASK 0x1 Interrupt not generated. MASK_GPIO1_8_RISEGPIO1_RISE_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. GPIO2_RISE_MASK 0x1 Interrupt not generated. GPIO2_RISE_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. GPIO3_RISE_MASK 0x1 Interrupt not generated. GPIO3_RISE_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. GPIO4_RISE_MASK 0x1 Interrupt not generated. GPIO4_RISE_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. GPIO5_RISE_MASK 0x1 Interrupt not generated. GPIO5_RISE_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. GPIO6_RISE_MASK 0x1 Interrupt not generated. GPIO6_RISE_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. GPIO7_RISE_MASK 0x1 Interrupt not generated. GPIO7_RISE_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. GPIO8_RISE_MASK 0x1 Interrupt not generated. GPIO8_RISE_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. MASK_GPIO9_11 / MASK_GPIO9_10 GPIO9_FALL_MASK 0x1 Interrupt not generated. MASK_GPIO9_11 / MASK_GPIO9_10GPIO9_FALL_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. GPIO9_RISE_MASK 0x1 Interrupt not generated. GPIO9_RISE_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. GPIO10_FALL_MASK 0x1 Interrupt not generated. GPIO10_FALL_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. GPIO11_FALL_MASK 0x1 Interrupt not generated. GPIO11_FALL_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. GPIO10_RISE_MASK 0x1 Interrupt not generated. GPIO10_RISE_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. GPIO11_RISE_MASK 0x1 Interrupt not generated. GPIO11_RISE_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. MASK_STARTUP NPWRON_START_MASK 0x1 Interrupt not generated. MASK_STARTUPNPWRON_START_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. ENABLE_MASK 0x0 Interrupt generated ENABLE_MASK 0x0 0x0 Interrupt generated Interrupt generated FSD_MASK 0x1 Interrupt not generated. FSD_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. SOFT_REBOOT_MASK 0x0 Interrupt generated SOFT_REBOOT_MASK 0x0 0x0 Interrupt generated Interrupt generated MASK_MISC TWARN_MASK 0x0 Interrupt generated MASK_MISCTWARN_MASK 0x0 0x0 Interrupt generated Interrupt generated BIST_PASS_MASK 0x0 Interrupt generated BIST_PASS_MASK 0x0 0x0 Interrupt generated Interrupt generated EXT_CLK_MASK 0x1 Interrupt not generated. EXT_CLK_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. MASK_MODERATE_ERR BIST_FAIL_MASK 0x0 Interrupt generated MASK_MODERATE_ERRBIST_FAIL_MASK 0x0 0x0 Interrupt generated Interrupt generated REG_CRC_ERR_MASK 0x0 Interrupt generated REG_CRC_ERR_MASK 0x0 0x0 Interrupt generated Interrupt generated SPMI_ERR_MASK 0x1 Interrupt not generated. SPMI_ERR_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. NPWRON_LONG_MASK 0x1 Interrupt not generated. NPWRON_LONG_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. NINT_READBACK_MASK 0x0 Interrupt generated NINT_READBACK_MASK 0x0 0x0 Interrupt generated Interrupt generated NRSTOUT_READBACK_ MASK 0x0 Interrupt generated NRSTOUT_READBACK_ MASK 0x0 0x0 Interrupt generated Interrupt generated MASK_FSM_ERR IMM_SHUTDOWN_MASK 0x0 Interrupt generated MASK_FSM_ERRIMM_SHUTDOWN_MASK 0x0 0x0 Interrupt generated Interrupt generated MCU_PWR_ERR_MASK 0x0 Interrupt generated MCU_PWR_ERR_MASK 0x0 0x0 Interrupt generated Interrupt generated SOC_PWR_ERR_MASK 0x0 Interrupt generated SOC_PWR_ERR_MASK 0x0 0x0 Interrupt generated Interrupt generated ORD_SHUTDOWN_MASK 0x0 Interrupt generated ORD_SHUTDOWN_MASK 0x0 0x0 Interrupt generated Interrupt generated MASK_COMM_ERR COMM_FRM_ERR_MASK 0x1 Interrupt not generated. MASK_COMM_ERRCOMM_FRM_ERR_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. COMM_CRC_ERR_MASK 0x0 Interrupt generated COMM_CRC_ERR_MASK 0x0 0x0 Interrupt generated Interrupt generated COMM_ADR_ERR_MASK 0x0 Interrupt generated COMM_ADR_ERR_MASK 0x0 0x0 Interrupt generated Interrupt generated I2C2_CRC_ERR_MASK 0x0 Interrupt generated I2C2_CRC_ERR_MASK 0x0 0x0 Interrupt generated Interrupt generated I2C2_ADR_ERR_MASK 0x0 Interrupt generated I2C2_ADR_ERR_MASK 0x0 0x0 Interrupt generated Interrupt generated MASK_READBACK_ERR EN_DRV_READBACK_ MASK 0x0 Interrupt generated MASK_READBACK_ERREN_DRV_READBACK_ MASK 0x0 0x0 Interrupt generated Interrupt generated NRSTOUT_SOC_ READBACK_MASK 0x1 Interrupt not generated. NRSTOUT_SOC_ READBACK_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. MASK_ESM ESM_SOC_PIN_MASK 0x1 Interrupt not generated. MASK_ESMESM_SOC_PIN_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. ESM_SOC_RST_MASK 0x1 Interrupt not generated. ESM_SOC_RST_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. ESM_SOC_FAIL_MASK 0x1 Interrupt not generated. ESM_SOC_FAIL_MASK 0x1 0x1 Interrupt not generated. Interrupt not generated. ESM_MCU_PIN_MASK 0x0 Interrupt generated ESM_MCU_PIN_MASK 0x0 0x0 Interrupt generated Interrupt generated ESM_MCU_RST_MASK 0x0 Interrupt generated ESM_MCU_RST_MASK 0x0 0x0 Interrupt generated Interrupt generated ESM_MCU_FAIL_MASK 0x0 Interrupt generated ESM_MCU_FAIL_MASK 0x0 0x0 Interrupt generated Interrupt generated GENERAL_REG_1 PFSM_ERR_MASK 0x0 Interrupt generated GENERAL_REG_1PFSM_ERR_MASK 0x0 0x0 Interrupt generated Interrupt generated POWERGOOD Settings These settings detail the default configurations for what is monitored by PGOOD pin. All these settings can be changed though I2C after startup. POWERGOOD NVM Settings Register Name Field Name TPS65931211-Q1 Value Description PGOOD_SEL_1 PGOOD_SEL_BUCK1 0x1 Voltage only PGOOD_SEL_BUCK2 0x1 Voltage only PGOOD_SEL_BUCK3 0x1 Voltage only PGOOD_SEL_BUCK4 0x1 Voltage only PGOOD_SEL_2 PGOOD_SEL_BUCK5 0x1 Voltage only PGOOD_SEL_3 PGOOD_SEL_LDO1 0x1 Voltage only PGOOD_SEL_LDO2 0x1 Voltage only PGOOD_SEL_LDO3 0x1 Voltage only PGOOD_SEL_LDO4 0x1 Voltage only PGOOD_SEL_4 PGOOD_SEL_VCCA 0x1 VCCA OV/UV threshold affecting PGOOD signal PGOOD_SEL_TDIE_WARN 0x1 Thermal warning affecting to PGOOD signal PGOOD_SEL_NRSTOUT 0x1 nRSTOUT pin low state forces PGOOD signal to low PGOOD_SEL_NRSTOUT_ SOC 0x0 Masked PGOOD_POL 0x0 PGOOD signal is high when monitored inputs are valid PGOOD_WINDOW 0x1 Both undervoltage and overvoltage are monitored POWERGOOD Settings These settings detail the default configurations for what is monitored by PGOOD pin. All these settings can be changed though I2C after startup. POWERGOOD NVM Settings Register Name Field Name TPS65931211-Q1 Value Description PGOOD_SEL_1 PGOOD_SEL_BUCK1 0x1 Voltage only PGOOD_SEL_BUCK2 0x1 Voltage only PGOOD_SEL_BUCK3 0x1 Voltage only PGOOD_SEL_BUCK4 0x1 Voltage only PGOOD_SEL_2 PGOOD_SEL_BUCK5 0x1 Voltage only PGOOD_SEL_3 PGOOD_SEL_LDO1 0x1 Voltage only PGOOD_SEL_LDO2 0x1 Voltage only PGOOD_SEL_LDO3 0x1 Voltage only PGOOD_SEL_LDO4 0x1 Voltage only PGOOD_SEL_4 PGOOD_SEL_VCCA 0x1 VCCA OV/UV threshold affecting PGOOD signal PGOOD_SEL_TDIE_WARN 0x1 Thermal warning affecting to PGOOD signal PGOOD_SEL_NRSTOUT 0x1 nRSTOUT pin low state forces PGOOD signal to low PGOOD_SEL_NRSTOUT_ SOC 0x0 Masked PGOOD_POL 0x0 PGOOD signal is high when monitored inputs are valid PGOOD_WINDOW 0x1 Both undervoltage and overvoltage are monitored These settings detail the default configurations for what is monitored by PGOOD pin. All these settings can be changed though I2C after startup. POWERGOOD NVM Settings Register Name Field Name TPS65931211-Q1 Value Description PGOOD_SEL_1 PGOOD_SEL_BUCK1 0x1 Voltage only PGOOD_SEL_BUCK2 0x1 Voltage only PGOOD_SEL_BUCK3 0x1 Voltage only PGOOD_SEL_BUCK4 0x1 Voltage only PGOOD_SEL_2 PGOOD_SEL_BUCK5 0x1 Voltage only PGOOD_SEL_3 PGOOD_SEL_LDO1 0x1 Voltage only PGOOD_SEL_LDO2 0x1 Voltage only PGOOD_SEL_LDO3 0x1 Voltage only PGOOD_SEL_LDO4 0x1 Voltage only PGOOD_SEL_4 PGOOD_SEL_VCCA 0x1 VCCA OV/UV threshold affecting PGOOD signal PGOOD_SEL_TDIE_WARN 0x1 Thermal warning affecting to PGOOD signal PGOOD_SEL_NRSTOUT 0x1 nRSTOUT pin low state forces PGOOD signal to low PGOOD_SEL_NRSTOUT_ SOC 0x0 Masked PGOOD_POL 0x0 PGOOD signal is high when monitored inputs are valid PGOOD_WINDOW 0x1 Both undervoltage and overvoltage are monitored These settings detail the default configurations for what is monitored by PGOOD pin. All these settings can be changed though I2C after startup.2 POWERGOOD NVM Settings Register Name Field Name TPS65931211-Q1 Value Description PGOOD_SEL_1 PGOOD_SEL_BUCK1 0x1 Voltage only PGOOD_SEL_BUCK2 0x1 Voltage only PGOOD_SEL_BUCK3 0x1 Voltage only PGOOD_SEL_BUCK4 0x1 Voltage only PGOOD_SEL_2 PGOOD_SEL_BUCK5 0x1 Voltage only PGOOD_SEL_3 PGOOD_SEL_LDO1 0x1 Voltage only PGOOD_SEL_LDO2 0x1 Voltage only PGOOD_SEL_LDO3 0x1 Voltage only PGOOD_SEL_LDO4 0x1 Voltage only PGOOD_SEL_4 PGOOD_SEL_VCCA 0x1 VCCA OV/UV threshold affecting PGOOD signal PGOOD_SEL_TDIE_WARN 0x1 Thermal warning affecting to PGOOD signal PGOOD_SEL_NRSTOUT 0x1 nRSTOUT pin low state forces PGOOD signal to low PGOOD_SEL_NRSTOUT_ SOC 0x0 Masked PGOOD_POL 0x0 PGOOD signal is high when monitored inputs are valid PGOOD_WINDOW 0x1 Both undervoltage and overvoltage are monitored POWERGOOD NVM Settings Register Name Field Name TPS65931211-Q1 Value Description PGOOD_SEL_1 PGOOD_SEL_BUCK1 0x1 Voltage only PGOOD_SEL_BUCK2 0x1 Voltage only PGOOD_SEL_BUCK3 0x1 Voltage only PGOOD_SEL_BUCK4 0x1 Voltage only PGOOD_SEL_2 PGOOD_SEL_BUCK5 0x1 Voltage only PGOOD_SEL_3 PGOOD_SEL_LDO1 0x1 Voltage only PGOOD_SEL_LDO2 0x1 Voltage only PGOOD_SEL_LDO3 0x1 Voltage only PGOOD_SEL_LDO4 0x1 Voltage only PGOOD_SEL_4 PGOOD_SEL_VCCA 0x1 VCCA OV/UV threshold affecting PGOOD signal PGOOD_SEL_TDIE_WARN 0x1 Thermal warning affecting to PGOOD signal PGOOD_SEL_NRSTOUT 0x1 nRSTOUT pin low state forces PGOOD signal to low PGOOD_SEL_NRSTOUT_ SOC 0x0 Masked PGOOD_POL 0x0 PGOOD signal is high when monitored inputs are valid PGOOD_WINDOW 0x1 Both undervoltage and overvoltage are monitored Register Name Field Name TPS65931211-Q1 Value Description Register Name Field Name TPS65931211-Q1 Register NameField Name TPS65931211-Q1 TPS65931211-Q1 Value Description ValueDescription PGOOD_SEL_1 PGOOD_SEL_BUCK1 0x1 Voltage only PGOOD_SEL_BUCK2 0x1 Voltage only PGOOD_SEL_BUCK3 0x1 Voltage only PGOOD_SEL_BUCK4 0x1 Voltage only PGOOD_SEL_2 PGOOD_SEL_BUCK5 0x1 Voltage only PGOOD_SEL_3 PGOOD_SEL_LDO1 0x1 Voltage only PGOOD_SEL_LDO2 0x1 Voltage only PGOOD_SEL_LDO3 0x1 Voltage only PGOOD_SEL_LDO4 0x1 Voltage only PGOOD_SEL_4 PGOOD_SEL_VCCA 0x1 VCCA OV/UV threshold affecting PGOOD signal PGOOD_SEL_TDIE_WARN 0x1 Thermal warning affecting to PGOOD signal PGOOD_SEL_NRSTOUT 0x1 nRSTOUT pin low state forces PGOOD signal to low PGOOD_SEL_NRSTOUT_ SOC 0x0 Masked PGOOD_POL 0x0 PGOOD signal is high when monitored inputs are valid PGOOD_WINDOW 0x1 Both undervoltage and overvoltage are monitored PGOOD_SEL_1 PGOOD_SEL_BUCK1 0x1 Voltage only PGOOD_SEL_1PGOOD_SEL_BUCK1 0x1 0x1 Voltage only Voltage only PGOOD_SEL_BUCK2 0x1 Voltage only PGOOD_SEL_BUCK2 0x1 0x1 Voltage only Voltage only PGOOD_SEL_BUCK3 0x1 Voltage only PGOOD_SEL_BUCK3 0x1 0x1 Voltage only Voltage only PGOOD_SEL_BUCK4 0x1 Voltage only PGOOD_SEL_BUCK4 0x1 0x1 Voltage only Voltage only PGOOD_SEL_2 PGOOD_SEL_BUCK5 0x1 Voltage only PGOOD_SEL_2PGOOD_SEL_BUCK5 0x1 0x1 Voltage only Voltage only PGOOD_SEL_3 PGOOD_SEL_LDO1 0x1 Voltage only PGOOD_SEL_3PGOOD_SEL_LDO1 0x1 0x1 Voltage only Voltage only PGOOD_SEL_LDO2 0x1 Voltage only PGOOD_SEL_LDO2 0x1 0x1 Voltage only Voltage only PGOOD_SEL_LDO3 0x1 Voltage only PGOOD_SEL_LDO3 0x1 0x1 Voltage only Voltage only PGOOD_SEL_LDO4 0x1 Voltage only PGOOD_SEL_LDO4 0x1 0x1 Voltage only Voltage only PGOOD_SEL_4 PGOOD_SEL_VCCA 0x1 VCCA OV/UV threshold affecting PGOOD signal PGOOD_SEL_4PGOOD_SEL_VCCA 0x1 0x1 VCCA OV/UV threshold affecting PGOOD signal VCCA OV/UV threshold affecting PGOOD signal PGOOD_SEL_TDIE_WARN 0x1 Thermal warning affecting to PGOOD signal PGOOD_SEL_TDIE_WARN 0x1 0x1 Thermal warning affecting to PGOOD signal Thermal warning affecting to PGOOD signal PGOOD_SEL_NRSTOUT 0x1 nRSTOUT pin low state forces PGOOD signal to low PGOOD_SEL_NRSTOUT 0x1 0x1 nRSTOUT pin low state forces PGOOD signal to low nRSTOUT pin low state forces PGOOD signal to low PGOOD_SEL_NRSTOUT_ SOC 0x0 Masked PGOOD_SEL_NRSTOUT_ SOC 0x0 0x0 Masked Masked PGOOD_POL 0x0 PGOOD signal is high when monitored inputs are valid PGOOD_POL 0x0 0x0 PGOOD signal is high when monitored inputs are valid PGOOD signal is high when monitored inputs are valid PGOOD_WINDOW 0x1 Both undervoltage and overvoltage are monitored PGOOD_WINDOW 0x1 0x1 Both undervoltage and overvoltage are monitored Both undervoltage and overvoltage are monitored Miscellaneous Settings These settings detail the default configurations of additional settings, such as spread spectrum, BUCK frequency, and LDO timeout. All these settings can be changed though I2C after startup. Miscellaneous NVM Settings Register Name Field Name TPS65931211-Q1 Value Description PLL_CTRL EXT_CLK_FREQ 0x0 1.1 MHz CONFIG_1 TWARN_LEVEL 0x1 140C I2C1_HS 0x0 Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode primary code. I2C2_HS 0x0 Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode primary code. EN_ILIM_FSM_CTRL 0x0 Buck/LDO regulators ILIM interrupts do not affect FSM triggers. NSLEEP1_MASK 0x1 NSLEEP1(B) does not affect FSM state transitions. NSLEEP2_MASK 0x0 NSLEEP2(B) affects FSM state transitions. CONFIG_2 BB_CHARGER_EN 0x0 Disabled BB_VEOC 0x0 2.5V BB_ICHR 0x0 100uA RECOV_CNT_REG_2 RECOV_CNT_THR 0xf 0xf BUCK_RESET_REG BUCK1_RESET 0x0 0x0 BUCK2_RESET 0x0 0x0 BUCK3_RESET 0x0 0x0 BUCK4_RESET 0x0 0x0 BUCK5_RESET 0x0 0x0 SPREAD_SPECTRUM_1 SS_EN 0x0 Spread spectrum disabled SS_MODE 0x1 Mixed dwell SS_DEPTH 0x0 No modulation SPREAD_SPECTRUM_2 SS_PARAM1 0x7 0x7 SS_PARAM2 0xc 0xc FREQ_SEL BUCK1_FREQ_SEL 0x0 2.2 MHz BUCK2_FREQ_SEL 0x0 2.2 MHz BUCK3_FREQ_SEL 0x0 2.2 MHz BUCK4_FREQ_SEL 0x0 2.2 MHz BUCK5_FREQ_SEL 0x0 2.2 MHz FSM_STEP_SIZE PFSM_DELAY_STEP 0xb 0xb LDO_RV_TIMEOUT_ REG_1 LDO1_RV_TIMEOUT 0xf 16ms LDO2_RV_TIMEOUT 0xf 16ms LDO_RV_TIMEOUT_ REG_2 LDO3_RV_TIMEOUT 0xf 16ms LDO4_RV_TIMEOUT 0xf 16ms USER_SPARE_REGS USER_SPARE_1 0x0 0x0 USER_SPARE_2 0x0 0x0 USER_SPARE_3 0x0 0x0 USER_SPARE_4 0x0 0x0 ESM_MCU_MODE_ CFG ESM_MCU_EN 0x0 ESM_MCU disabled. ESM_SOC_MODE_ CFG ESM_SOC_EN 0x0 ESM_SoC disabled. CUSTOMER_NVM_ID_REG CUSTOMER_NVM_ID 0x0 0x0 RTC_CTRL_2 XTAL_EN 0x0 Crystal oscillator is disabled LP_STANDBY_SEL 0x0 LDOINT is enabled in standby state. FAST_BIST 0x0 Logic and analog BIST is run at BOOT BIST. STARTUP_DEST 0x3 ACTIVE XTAL_SEL 0x0 6 pF PFSM_DELAY_REG_1 PFSM_DELAY1 0x0 0x0 PFSM_DELAY_REG_2 PFSM_DELAY2 0x0 0x0 PFSM_DELAY_REG_3 PFSM_DELAY3 0x0 0x0 PFSM_DELAY_REG_4 PFSM_DELAY4 0x0 0x0 GENERAL_REG_0 FAST_BOOT_BIST 0x0 LBIST is run during boot BIST GENERAL_REG_1 REG_CRC_EN 0x0 Register CRC disabled Miscellaneous Settings These settings detail the default configurations of additional settings, such as spread spectrum, BUCK frequency, and LDO timeout. All these settings can be changed though I2C after startup. Miscellaneous NVM Settings Register Name Field Name TPS65931211-Q1 Value Description PLL_CTRL EXT_CLK_FREQ 0x0 1.1 MHz CONFIG_1 TWARN_LEVEL 0x1 140C I2C1_HS 0x0 Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode primary code. I2C2_HS 0x0 Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode primary code. EN_ILIM_FSM_CTRL 0x0 Buck/LDO regulators ILIM interrupts do not affect FSM triggers. NSLEEP1_MASK 0x1 NSLEEP1(B) does not affect FSM state transitions. NSLEEP2_MASK 0x0 NSLEEP2(B) affects FSM state transitions. CONFIG_2 BB_CHARGER_EN 0x0 Disabled BB_VEOC 0x0 2.5V BB_ICHR 0x0 100uA RECOV_CNT_REG_2 RECOV_CNT_THR 0xf 0xf BUCK_RESET_REG BUCK1_RESET 0x0 0x0 BUCK2_RESET 0x0 0x0 BUCK3_RESET 0x0 0x0 BUCK4_RESET 0x0 0x0 BUCK5_RESET 0x0 0x0 SPREAD_SPECTRUM_1 SS_EN 0x0 Spread spectrum disabled SS_MODE 0x1 Mixed dwell SS_DEPTH 0x0 No modulation SPREAD_SPECTRUM_2 SS_PARAM1 0x7 0x7 SS_PARAM2 0xc 0xc FREQ_SEL BUCK1_FREQ_SEL 0x0 2.2 MHz BUCK2_FREQ_SEL 0x0 2.2 MHz BUCK3_FREQ_SEL 0x0 2.2 MHz BUCK4_FREQ_SEL 0x0 2.2 MHz BUCK5_FREQ_SEL 0x0 2.2 MHz FSM_STEP_SIZE PFSM_DELAY_STEP 0xb 0xb LDO_RV_TIMEOUT_ REG_1 LDO1_RV_TIMEOUT 0xf 16ms LDO2_RV_TIMEOUT 0xf 16ms LDO_RV_TIMEOUT_ REG_2 LDO3_RV_TIMEOUT 0xf 16ms LDO4_RV_TIMEOUT 0xf 16ms USER_SPARE_REGS USER_SPARE_1 0x0 0x0 USER_SPARE_2 0x0 0x0 USER_SPARE_3 0x0 0x0 USER_SPARE_4 0x0 0x0 ESM_MCU_MODE_ CFG ESM_MCU_EN 0x0 ESM_MCU disabled. ESM_SOC_MODE_ CFG ESM_SOC_EN 0x0 ESM_SoC disabled. CUSTOMER_NVM_ID_REG CUSTOMER_NVM_ID 0x0 0x0 RTC_CTRL_2 XTAL_EN 0x0 Crystal oscillator is disabled LP_STANDBY_SEL 0x0 LDOINT is enabled in standby state. FAST_BIST 0x0 Logic and analog BIST is run at BOOT BIST. STARTUP_DEST 0x3 ACTIVE XTAL_SEL 0x0 6 pF PFSM_DELAY_REG_1 PFSM_DELAY1 0x0 0x0 PFSM_DELAY_REG_2 PFSM_DELAY2 0x0 0x0 PFSM_DELAY_REG_3 PFSM_DELAY3 0x0 0x0 PFSM_DELAY_REG_4 PFSM_DELAY4 0x0 0x0 GENERAL_REG_0 FAST_BOOT_BIST 0x0 LBIST is run during boot BIST GENERAL_REG_1 REG_CRC_EN 0x0 Register CRC disabled These settings detail the default configurations of additional settings, such as spread spectrum, BUCK frequency, and LDO timeout. All these settings can be changed though I2C after startup. Miscellaneous NVM Settings Register Name Field Name TPS65931211-Q1 Value Description PLL_CTRL EXT_CLK_FREQ 0x0 1.1 MHz CONFIG_1 TWARN_LEVEL 0x1 140C I2C1_HS 0x0 Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode primary code. I2C2_HS 0x0 Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode primary code. EN_ILIM_FSM_CTRL 0x0 Buck/LDO regulators ILIM interrupts do not affect FSM triggers. NSLEEP1_MASK 0x1 NSLEEP1(B) does not affect FSM state transitions. NSLEEP2_MASK 0x0 NSLEEP2(B) affects FSM state transitions. CONFIG_2 BB_CHARGER_EN 0x0 Disabled BB_VEOC 0x0 2.5V BB_ICHR 0x0 100uA RECOV_CNT_REG_2 RECOV_CNT_THR 0xf 0xf BUCK_RESET_REG BUCK1_RESET 0x0 0x0 BUCK2_RESET 0x0 0x0 BUCK3_RESET 0x0 0x0 BUCK4_RESET 0x0 0x0 BUCK5_RESET 0x0 0x0 SPREAD_SPECTRUM_1 SS_EN 0x0 Spread spectrum disabled SS_MODE 0x1 Mixed dwell SS_DEPTH 0x0 No modulation SPREAD_SPECTRUM_2 SS_PARAM1 0x7 0x7 SS_PARAM2 0xc 0xc FREQ_SEL BUCK1_FREQ_SEL 0x0 2.2 MHz BUCK2_FREQ_SEL 0x0 2.2 MHz BUCK3_FREQ_SEL 0x0 2.2 MHz BUCK4_FREQ_SEL 0x0 2.2 MHz BUCK5_FREQ_SEL 0x0 2.2 MHz FSM_STEP_SIZE PFSM_DELAY_STEP 0xb 0xb LDO_RV_TIMEOUT_ REG_1 LDO1_RV_TIMEOUT 0xf 16ms LDO2_RV_TIMEOUT 0xf 16ms LDO_RV_TIMEOUT_ REG_2 LDO3_RV_TIMEOUT 0xf 16ms LDO4_RV_TIMEOUT 0xf 16ms USER_SPARE_REGS USER_SPARE_1 0x0 0x0 USER_SPARE_2 0x0 0x0 USER_SPARE_3 0x0 0x0 USER_SPARE_4 0x0 0x0 ESM_MCU_MODE_ CFG ESM_MCU_EN 0x0 ESM_MCU disabled. ESM_SOC_MODE_ CFG ESM_SOC_EN 0x0 ESM_SoC disabled. CUSTOMER_NVM_ID_REG CUSTOMER_NVM_ID 0x0 0x0 RTC_CTRL_2 XTAL_EN 0x0 Crystal oscillator is disabled LP_STANDBY_SEL 0x0 LDOINT is enabled in standby state. FAST_BIST 0x0 Logic and analog BIST is run at BOOT BIST. STARTUP_DEST 0x3 ACTIVE XTAL_SEL 0x0 6 pF PFSM_DELAY_REG_1 PFSM_DELAY1 0x0 0x0 PFSM_DELAY_REG_2 PFSM_DELAY2 0x0 0x0 PFSM_DELAY_REG_3 PFSM_DELAY3 0x0 0x0 PFSM_DELAY_REG_4 PFSM_DELAY4 0x0 0x0 GENERAL_REG_0 FAST_BOOT_BIST 0x0 LBIST is run during boot BIST GENERAL_REG_1 REG_CRC_EN 0x0 Register CRC disabled These settings detail the default configurations of additional settings, such as spread spectrum, BUCK frequency, and LDO timeout. All these settings can be changed though I2C after startup.2 Miscellaneous NVM Settings Register Name Field Name TPS65931211-Q1 Value Description PLL_CTRL EXT_CLK_FREQ 0x0 1.1 MHz CONFIG_1 TWARN_LEVEL 0x1 140C I2C1_HS 0x0 Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode primary code. I2C2_HS 0x0 Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode primary code. EN_ILIM_FSM_CTRL 0x0 Buck/LDO regulators ILIM interrupts do not affect FSM triggers. NSLEEP1_MASK 0x1 NSLEEP1(B) does not affect FSM state transitions. NSLEEP2_MASK 0x0 NSLEEP2(B) affects FSM state transitions. CONFIG_2 BB_CHARGER_EN 0x0 Disabled BB_VEOC 0x0 2.5V BB_ICHR 0x0 100uA RECOV_CNT_REG_2 RECOV_CNT_THR 0xf 0xf BUCK_RESET_REG BUCK1_RESET 0x0 0x0 BUCK2_RESET 0x0 0x0 BUCK3_RESET 0x0 0x0 BUCK4_RESET 0x0 0x0 BUCK5_RESET 0x0 0x0 SPREAD_SPECTRUM_1 SS_EN 0x0 Spread spectrum disabled SS_MODE 0x1 Mixed dwell SS_DEPTH 0x0 No modulation SPREAD_SPECTRUM_2 SS_PARAM1 0x7 0x7 SS_PARAM2 0xc 0xc FREQ_SEL BUCK1_FREQ_SEL 0x0 2.2 MHz BUCK2_FREQ_SEL 0x0 2.2 MHz BUCK3_FREQ_SEL 0x0 2.2 MHz BUCK4_FREQ_SEL 0x0 2.2 MHz BUCK5_FREQ_SEL 0x0 2.2 MHz FSM_STEP_SIZE PFSM_DELAY_STEP 0xb 0xb LDO_RV_TIMEOUT_ REG_1 LDO1_RV_TIMEOUT 0xf 16ms LDO2_RV_TIMEOUT 0xf 16ms LDO_RV_TIMEOUT_ REG_2 LDO3_RV_TIMEOUT 0xf 16ms LDO4_RV_TIMEOUT 0xf 16ms USER_SPARE_REGS USER_SPARE_1 0x0 0x0 USER_SPARE_2 0x0 0x0 USER_SPARE_3 0x0 0x0 USER_SPARE_4 0x0 0x0 ESM_MCU_MODE_ CFG ESM_MCU_EN 0x0 ESM_MCU disabled. ESM_SOC_MODE_ CFG ESM_SOC_EN 0x0 ESM_SoC disabled. CUSTOMER_NVM_ID_REG CUSTOMER_NVM_ID 0x0 0x0 RTC_CTRL_2 XTAL_EN 0x0 Crystal oscillator is disabled LP_STANDBY_SEL 0x0 LDOINT is enabled in standby state. FAST_BIST 0x0 Logic and analog BIST is run at BOOT BIST. STARTUP_DEST 0x3 ACTIVE XTAL_SEL 0x0 6 pF PFSM_DELAY_REG_1 PFSM_DELAY1 0x0 0x0 PFSM_DELAY_REG_2 PFSM_DELAY2 0x0 0x0 PFSM_DELAY_REG_3 PFSM_DELAY3 0x0 0x0 PFSM_DELAY_REG_4 PFSM_DELAY4 0x0 0x0 GENERAL_REG_0 FAST_BOOT_BIST 0x0 LBIST is run during boot BIST GENERAL_REG_1 REG_CRC_EN 0x0 Register CRC disabled Miscellaneous NVM Settings Register Name Field Name TPS65931211-Q1 Value Description PLL_CTRL EXT_CLK_FREQ 0x0 1.1 MHz CONFIG_1 TWARN_LEVEL 0x1 140C I2C1_HS 0x0 Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode primary code. I2C2_HS 0x0 Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode primary code. EN_ILIM_FSM_CTRL 0x0 Buck/LDO regulators ILIM interrupts do not affect FSM triggers. NSLEEP1_MASK 0x1 NSLEEP1(B) does not affect FSM state transitions. NSLEEP2_MASK 0x0 NSLEEP2(B) affects FSM state transitions. CONFIG_2 BB_CHARGER_EN 0x0 Disabled BB_VEOC 0x0 2.5V BB_ICHR 0x0 100uA RECOV_CNT_REG_2 RECOV_CNT_THR 0xf 0xf BUCK_RESET_REG BUCK1_RESET 0x0 0x0 BUCK2_RESET 0x0 0x0 BUCK3_RESET 0x0 0x0 BUCK4_RESET 0x0 0x0 BUCK5_RESET 0x0 0x0 SPREAD_SPECTRUM_1 SS_EN 0x0 Spread spectrum disabled SS_MODE 0x1 Mixed dwell SS_DEPTH 0x0 No modulation SPREAD_SPECTRUM_2 SS_PARAM1 0x7 0x7 SS_PARAM2 0xc 0xc FREQ_SEL BUCK1_FREQ_SEL 0x0 2.2 MHz BUCK2_FREQ_SEL 0x0 2.2 MHz BUCK3_FREQ_SEL 0x0 2.2 MHz BUCK4_FREQ_SEL 0x0 2.2 MHz BUCK5_FREQ_SEL 0x0 2.2 MHz FSM_STEP_SIZE PFSM_DELAY_STEP 0xb 0xb LDO_RV_TIMEOUT_ REG_1 LDO1_RV_TIMEOUT 0xf 16ms LDO2_RV_TIMEOUT 0xf 16ms LDO_RV_TIMEOUT_ REG_2 LDO3_RV_TIMEOUT 0xf 16ms LDO4_RV_TIMEOUT 0xf 16ms USER_SPARE_REGS USER_SPARE_1 0x0 0x0 USER_SPARE_2 0x0 0x0 USER_SPARE_3 0x0 0x0 USER_SPARE_4 0x0 0x0 ESM_MCU_MODE_ CFG ESM_MCU_EN 0x0 ESM_MCU disabled. ESM_SOC_MODE_ CFG ESM_SOC_EN 0x0 ESM_SoC disabled. CUSTOMER_NVM_ID_REG CUSTOMER_NVM_ID 0x0 0x0 RTC_CTRL_2 XTAL_EN 0x0 Crystal oscillator is disabled LP_STANDBY_SEL 0x0 LDOINT is enabled in standby state. FAST_BIST 0x0 Logic and analog BIST is run at BOOT BIST. STARTUP_DEST 0x3 ACTIVE XTAL_SEL 0x0 6 pF PFSM_DELAY_REG_1 PFSM_DELAY1 0x0 0x0 PFSM_DELAY_REG_2 PFSM_DELAY2 0x0 0x0 PFSM_DELAY_REG_3 PFSM_DELAY3 0x0 0x0 PFSM_DELAY_REG_4 PFSM_DELAY4 0x0 0x0 GENERAL_REG_0 FAST_BOOT_BIST 0x0 LBIST is run during boot BIST GENERAL_REG_1 REG_CRC_EN 0x0 Register CRC disabled Register Name Field Name TPS65931211-Q1 Value Description Register Name Field Name TPS65931211-Q1 Register NameField Name TPS65931211-Q1 TPS65931211-Q1 Value Description ValueDescription PLL_CTRL EXT_CLK_FREQ 0x0 1.1 MHz CONFIG_1 TWARN_LEVEL 0x1 140C I2C1_HS 0x0 Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode primary code. I2C2_HS 0x0 Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode primary code. EN_ILIM_FSM_CTRL 0x0 Buck/LDO regulators ILIM interrupts do not affect FSM triggers. NSLEEP1_MASK 0x1 NSLEEP1(B) does not affect FSM state transitions. NSLEEP2_MASK 0x0 NSLEEP2(B) affects FSM state transitions. CONFIG_2 BB_CHARGER_EN 0x0 Disabled BB_VEOC 0x0 2.5V BB_ICHR 0x0 100uA RECOV_CNT_REG_2 RECOV_CNT_THR 0xf 0xf BUCK_RESET_REG BUCK1_RESET 0x0 0x0 BUCK2_RESET 0x0 0x0 BUCK3_RESET 0x0 0x0 BUCK4_RESET 0x0 0x0 BUCK5_RESET 0x0 0x0 SPREAD_SPECTRUM_1 SS_EN 0x0 Spread spectrum disabled SS_MODE 0x1 Mixed dwell SS_DEPTH 0x0 No modulation SPREAD_SPECTRUM_2 SS_PARAM1 0x7 0x7 SS_PARAM2 0xc 0xc FREQ_SEL BUCK1_FREQ_SEL 0x0 2.2 MHz BUCK2_FREQ_SEL 0x0 2.2 MHz BUCK3_FREQ_SEL 0x0 2.2 MHz BUCK4_FREQ_SEL 0x0 2.2 MHz BUCK5_FREQ_SEL 0x0 2.2 MHz FSM_STEP_SIZE PFSM_DELAY_STEP 0xb 0xb LDO_RV_TIMEOUT_ REG_1 LDO1_RV_TIMEOUT 0xf 16ms LDO2_RV_TIMEOUT 0xf 16ms LDO_RV_TIMEOUT_ REG_2 LDO3_RV_TIMEOUT 0xf 16ms LDO4_RV_TIMEOUT 0xf 16ms USER_SPARE_REGS USER_SPARE_1 0x0 0x0 USER_SPARE_2 0x0 0x0 USER_SPARE_3 0x0 0x0 USER_SPARE_4 0x0 0x0 ESM_MCU_MODE_ CFG ESM_MCU_EN 0x0 ESM_MCU disabled. ESM_SOC_MODE_ CFG ESM_SOC_EN 0x0 ESM_SoC disabled. CUSTOMER_NVM_ID_REG CUSTOMER_NVM_ID 0x0 0x0 RTC_CTRL_2 XTAL_EN 0x0 Crystal oscillator is disabled LP_STANDBY_SEL 0x0 LDOINT is enabled in standby state. FAST_BIST 0x0 Logic and analog BIST is run at BOOT BIST. STARTUP_DEST 0x3 ACTIVE XTAL_SEL 0x0 6 pF PFSM_DELAY_REG_1 PFSM_DELAY1 0x0 0x0 PFSM_DELAY_REG_2 PFSM_DELAY2 0x0 0x0 PFSM_DELAY_REG_3 PFSM_DELAY3 0x0 0x0 PFSM_DELAY_REG_4 PFSM_DELAY4 0x0 0x0 GENERAL_REG_0 FAST_BOOT_BIST 0x0 LBIST is run during boot BIST GENERAL_REG_1 REG_CRC_EN 0x0 Register CRC disabled PLL_CTRL EXT_CLK_FREQ 0x0 1.1 MHz PLL_CTRLEXT_CLK_FREQ 0x0 0x0 1.1 MHz 1.1 MHz CONFIG_1 TWARN_LEVEL 0x1 140C CONFIG_1TWARN_LEVEL 0x1 0x1 140C 140C I2C1_HS 0x0 Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode primary code. I2C1_HS 0x0 0x0 Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode primary code. Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode primary code. I2C2_HS 0x0 Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode primary code. I2C2_HS 0x0 0x0 Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode primary code. Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode primary code. EN_ILIM_FSM_CTRL 0x0 Buck/LDO regulators ILIM interrupts do not affect FSM triggers. EN_ILIM_FSM_CTRL 0x0 0x0 Buck/LDO regulators ILIM interrupts do not affect FSM triggers. Buck/LDO regulators ILIM interrupts do not affect FSM triggers. NSLEEP1_MASK 0x1 NSLEEP1(B) does not affect FSM state transitions. NSLEEP1_MASK 0x1 0x1 NSLEEP1(B) does not affect FSM state transitions. NSLEEP1(B) does not affect FSM state transitions. NSLEEP2_MASK 0x0 NSLEEP2(B) affects FSM state transitions. NSLEEP2_MASK 0x0 0x0 NSLEEP2(B) affects FSM state transitions. NSLEEP2(B) affects FSM state transitions. CONFIG_2 BB_CHARGER_EN 0x0 Disabled CONFIG_2BB_CHARGER_EN 0x0 0x0 Disabled Disabled BB_VEOC 0x0 2.5V BB_VEOC 0x0 0x0 2.5V 2.5V BB_ICHR 0x0 100uA BB_ICHR 0x0 0x0 100uA 100uA RECOV_CNT_REG_2 RECOV_CNT_THR 0xf 0xf RECOV_CNT_REG_2RECOV_CNT_THR 0xf 0xf 0xf 0xf BUCK_RESET_REG BUCK1_RESET 0x0 0x0 BUCK_RESET_REGBUCK1_RESET 0x0 0x0 0x0 0x0 BUCK2_RESET 0x0 0x0 BUCK2_RESET 0x0 0x0 0x0 0x0 BUCK3_RESET 0x0 0x0 BUCK3_RESET 0x0 0x0 0x0 0x0 BUCK4_RESET 0x0 0x0 BUCK4_RESET 0x0 0x0 0x0 0x0 BUCK5_RESET 0x0 0x0 BUCK5_RESET 0x0 0x0 0x0 0x0 SPREAD_SPECTRUM_1 SS_EN 0x0 Spread spectrum disabled SPREAD_SPECTRUM_1SS_EN 0x0 0x0 Spread spectrum disabled Spread spectrum disabled SS_MODE 0x1 Mixed dwell SS_MODE 0x1 0x1 Mixed dwell Mixed dwell SS_DEPTH 0x0 No modulation SS_DEPTH 0x0 0x0 No modulation No modulation SPREAD_SPECTRUM_2 SS_PARAM1 0x7 0x7 SPREAD_SPECTRUM_2SS_PARAM1 0x7 0x7 0x7 0x7 SS_PARAM2 0xc 0xc SS_PARAM2 0xc 0xc 0xc 0xc FREQ_SEL BUCK1_FREQ_SEL 0x0 2.2 MHz FREQ_SELBUCK1_FREQ_SEL 0x0 0x0 2.2 MHz 2.2 MHz BUCK2_FREQ_SEL 0x0 2.2 MHz BUCK2_FREQ_SEL 0x0 0x0 2.2 MHz 2.2 MHz BUCK3_FREQ_SEL 0x0 2.2 MHz BUCK3_FREQ_SEL 0x0 0x0 2.2 MHz 2.2 MHz BUCK4_FREQ_SEL 0x0 2.2 MHz BUCK4_FREQ_SEL 0x0 0x0 2.2 MHz 2.2 MHz BUCK5_FREQ_SEL 0x0 2.2 MHz BUCK5_FREQ_SEL 0x0 0x0 2.2 MHz 2.2 MHz FSM_STEP_SIZE PFSM_DELAY_STEP 0xb 0xb FSM_STEP_SIZEPFSM_DELAY_STEP 0xb 0xb 0xb 0xb LDO_RV_TIMEOUT_ REG_1 LDO1_RV_TIMEOUT 0xf 16ms LDO_RV_TIMEOUT_ REG_1LDO1_RV_TIMEOUT 0xf 0xf 16ms 16ms LDO2_RV_TIMEOUT 0xf 16ms LDO2_RV_TIMEOUT 0xf 0xf 16ms 16ms LDO_RV_TIMEOUT_ REG_2 LDO3_RV_TIMEOUT 0xf 16ms LDO_RV_TIMEOUT_ REG_2LDO3_RV_TIMEOUT 0xf 0xf 16ms 16ms LDO4_RV_TIMEOUT 0xf 16ms LDO4_RV_TIMEOUT 0xf 0xf 16ms 16ms USER_SPARE_REGS USER_SPARE_1 0x0 0x0 USER_SPARE_REGSUSER_SPARE_1 0x0 0x0 0x0 0x0 USER_SPARE_2 0x0 0x0 USER_SPARE_2 0x0 0x0 0x0 0x0 USER_SPARE_3 0x0 0x0 USER_SPARE_3 0x0 0x0 0x0 0x0 USER_SPARE_4 0x0 0x0 USER_SPARE_4 0x0 0x0 0x0 0x0 ESM_MCU_MODE_ CFG ESM_MCU_EN 0x0 ESM_MCU disabled. ESM_MCU_MODE_ CFGESM_MCU_EN 0x0 0x0 ESM_MCU disabled. ESM_MCU disabled. ESM_SOC_MODE_ CFG ESM_SOC_EN 0x0 ESM_SoC disabled. ESM_SOC_MODE_ CFGESM_SOC_EN 0x0 0x0 ESM_SoC disabled. ESM_SoC disabled. CUSTOMER_NVM_ID_REG CUSTOMER_NVM_ID 0x0 0x0 CUSTOMER_NVM_ID_REGCUSTOMER_NVM_ID 0x0 0x0 0x0 0x0 RTC_CTRL_2 XTAL_EN 0x0 Crystal oscillator is disabled RTC_CTRL_2XTAL_EN 0x0 0x0 Crystal oscillator is disabled Crystal oscillator is disabled LP_STANDBY_SEL 0x0 LDOINT is enabled in standby state. LP_STANDBY_SEL 0x0 0x0 LDOINT is enabled in standby state. LDOINT is enabled in standby state. FAST_BIST 0x0 Logic and analog BIST is run at BOOT BIST. FAST_BIST 0x0 0x0 Logic and analog BIST is run at BOOT BIST. Logic and analog BIST is run at BOOT BIST. STARTUP_DEST 0x3 ACTIVE STARTUP_DEST 0x3 0x3 ACTIVE ACTIVE XTAL_SEL 0x0 6 pF XTAL_SEL 0x0 0x0 6 pF 6 pF PFSM_DELAY_REG_1 PFSM_DELAY1 0x0 0x0 PFSM_DELAY_REG_1PFSM_DELAY1 0x0 0x0 0x0 0x0 PFSM_DELAY_REG_2 PFSM_DELAY2 0x0 0x0 PFSM_DELAY_REG_2PFSM_DELAY2 0x0 0x0 0x0 0x0 PFSM_DELAY_REG_3 PFSM_DELAY3 0x0 0x0 PFSM_DELAY_REG_3PFSM_DELAY3 0x0 0x0 0x0 0x0 PFSM_DELAY_REG_4 PFSM_DELAY4 0x0 0x0 PFSM_DELAY_REG_4PFSM_DELAY4 0x0 0x0 0x0 0x0 GENERAL_REG_0 FAST_BOOT_BIST 0x0 LBIST is run during boot BIST GENERAL_REG_0FAST_BOOT_BIST 0x0 0x0 LBIST is run during boot BIST LBIST is run during boot BIST GENERAL_REG_1 REG_CRC_EN 0x0 Register CRC disabled GENERAL_REG_1REG_CRC_EN 0x0 0x0 Register CRC disabled Register CRC disabled Interface Settings These settings detail the default interface, interface configurations, and device addresses. These settings cannot be changed after device startup. Interface NVM Settings Register Name Field Name TPS65931211-Q1 Value Description SERIAL_IF_CONFIG I2C_SPI_SEL 0x0 I2C I2C1_SPI_CRC_EN 0x0 CRC disabled I2C2_CRC_EN 0x0 CRC disabled I2C1_ID_REG I2C1_ID 0x48 0x48 I2C2_ID_REG I2C2_ID 0x12 0x12 Interface Settings These settings detail the default interface, interface configurations, and device addresses. These settings cannot be changed after device startup. Interface NVM Settings Register Name Field Name TPS65931211-Q1 Value Description SERIAL_IF_CONFIG I2C_SPI_SEL 0x0 I2C I2C1_SPI_CRC_EN 0x0 CRC disabled I2C2_CRC_EN 0x0 CRC disabled I2C1_ID_REG I2C1_ID 0x48 0x48 I2C2_ID_REG I2C2_ID 0x12 0x12 These settings detail the default interface, interface configurations, and device addresses. These settings cannot be changed after device startup. Interface NVM Settings Register Name Field Name TPS65931211-Q1 Value Description SERIAL_IF_CONFIG I2C_SPI_SEL 0x0 I2C I2C1_SPI_CRC_EN 0x0 CRC disabled I2C2_CRC_EN 0x0 CRC disabled I2C1_ID_REG I2C1_ID 0x48 0x48 I2C2_ID_REG I2C2_ID 0x12 0x12 These settings detail the default interface, interface configurations, and device addresses. These settings cannot be changed after device startup. Interface NVM Settings Register Name Field Name TPS65931211-Q1 Value Description SERIAL_IF_CONFIG I2C_SPI_SEL 0x0 I2C I2C1_SPI_CRC_EN 0x0 CRC disabled I2C2_CRC_EN 0x0 CRC disabled I2C1_ID_REG I2C1_ID 0x48 0x48 I2C2_ID_REG I2C2_ID 0x12 0x12 Interface NVM Settings Register Name Field Name TPS65931211-Q1 Value Description SERIAL_IF_CONFIG I2C_SPI_SEL 0x0 I2C I2C1_SPI_CRC_EN 0x0 CRC disabled I2C2_CRC_EN 0x0 CRC disabled I2C1_ID_REG I2C1_ID 0x48 0x48 I2C2_ID_REG I2C2_ID 0x12 0x12 Register Name Field Name TPS65931211-Q1 Value Description Register Name Field Name TPS65931211-Q1 Register NameField Name TPS65931211-Q1 TPS65931211-Q1 Value Description ValueDescription SERIAL_IF_CONFIG I2C_SPI_SEL 0x0 I2C I2C1_SPI_CRC_EN 0x0 CRC disabled I2C2_CRC_EN 0x0 CRC disabled I2C1_ID_REG I2C1_ID 0x48 0x48 I2C2_ID_REG I2C2_ID 0x12 0x12 SERIAL_IF_CONFIG I2C_SPI_SEL 0x0 I2C SERIAL_IF_CONFIGI2C_SPI_SEL 0x0 0x0 I2C I2C I2C1_SPI_CRC_EN 0x0 CRC disabled I2C1_SPI_CRC_EN 0x0 0x0 CRC disabled CRC disabled I2C2_CRC_EN 0x0 CRC disabled I2C2_CRC_EN 0x0 0x0 CRC disabled CRC disabled I2C1_ID_REG I2C1_ID 0x48 0x48 I2C1_ID_REGI2C1_ID 0x48 0x48 0x48 0x48 I2C2_ID_REG I2C2_ID 0x12 0x12 I2C2_ID_REGI2C2_ID 0x12 0x12 0x12 0x12 Watchdog Settings These settings detail the default watchdog addresses. These settings can be changed though I2C after startup. Watchdog NVM Settings Register Name Field Name TPS65931211-Q1 Value Description WD_LONGWIN_CFG WD_LONGWIN 0xff 0xff WD_THR_CFG WD_EN 0x1 Watchdog enabled. Watchdog Settings These settings detail the default watchdog addresses. These settings can be changed though I2C after startup. Watchdog NVM Settings Register Name Field Name TPS65931211-Q1 Value Description WD_LONGWIN_CFG WD_LONGWIN 0xff 0xff WD_THR_CFG WD_EN 0x1 Watchdog enabled. These settings detail the default watchdog addresses. These settings can be changed though I2C after startup. Watchdog NVM Settings Register Name Field Name TPS65931211-Q1 Value Description WD_LONGWIN_CFG WD_LONGWIN 0xff 0xff WD_THR_CFG WD_EN 0x1 Watchdog enabled. These settings detail the default watchdog addresses. These settings can be changed though I2C after startup.2 Watchdog NVM Settings Register Name Field Name TPS65931211-Q1 Value Description WD_LONGWIN_CFG WD_LONGWIN 0xff 0xff WD_THR_CFG WD_EN 0x1 Watchdog enabled. Watchdog NVM Settings Register Name Field Name TPS65931211-Q1 Value Description WD_LONGWIN_CFG WD_LONGWIN 0xff 0xff WD_THR_CFG WD_EN 0x1 Watchdog enabled. Register Name Field Name TPS65931211-Q1 Value Description Register Name Field Name TPS65931211-Q1 Register NameField Name TPS65931211-Q1 TPS65931211-Q1 Value Description ValueDescription WD_LONGWIN_CFG WD_LONGWIN 0xff 0xff WD_THR_CFG WD_EN 0x1 Watchdog enabled. WD_LONGWIN_CFG WD_LONGWIN 0xff 0xff WD_LONGWIN_CFGWD_LONGWIN 0xff 0xff 0xff 0xff WD_THR_CFG WD_EN 0x1 Watchdog enabled. WD_THR_CFGWD_EN 0x1 0x1 Watchdog enabled. Watchdog enabled. Pre-Configurable Finite State Machine (PFSM) Settings This section describes the default PFSM settings of the TPS65931211-Q1 devices. These settings cannot be changed after device startup. Configured States In this PDN, the PMIC have the following configured power states: PFSM_START wait4Enable Active (Active SoC) S2R (IO + DDR) Standby (Partial IO, PMIC OFF) TO_SAFE shows the configured PDN power states along with the transition conditions to move between the states. Additionally, the transitions to hardware states, such as SAFE RECOVERY and LP_STANDBY are shown. The hardware states are part of the fixed device power Finite State Machine (FSM) and described in the TPS6593-Q1 data sheet, see . Pre-Configurable Finite State Machine (PFSM) Mission States and Transitions When the PMICs transition from the FSM to the PFSM, it waits for a valid ON Request before entering the ACTIVE state. The definition for each power state is described below: PFSM_START PFSM_START is the first state of the pre-configurable mission states. In this state the PMIC is powered by a valid supply. This state is entered when PMIC transitions from the FSM into PFSM. Once the PMIC arrives the PFSM_START, it waits for a valid ON request before transitioning to the next state. ACTIVE The PMIC is powered by a valid supply. The PMIC is fully functional and supply power to all PDN loads. The processor has completed a recommended power up sequence with all voltage domains energized. Refer to the sequence description. S2R The PMIC is powered by a valid supply. When the GPIO3 (nSLEEP2) is pulled low, only the power resources assigned to the 1.8V IO domain (Buck5) and the DDR (Buck4) are energized while all other domains are OFF to minimize total system power. EN_DRV is forced low in this state. This state supports the IO+DDR (suspend to RAM) low power mode on the AM62A. STANDBY The PMIC is powered by a valid supply on the system power rail (VCCA > VCCA_UV). All device resources are powered down in the STANDBY state. EN_DRV is forced low in this state. The processor is in the Off state, no voltage domains are energized. Refer to the sequence description. TO_SAFE If there is an event which causes MODERATE_ERR_INT = '1' or severe error from any of the previous described states, PMIC executes a orderly or immediate sequence and transitions out of the PFSM onto the FSM. MCU power errors and moderate errors result in the orderly shutdown trigger. Severe errors result in the immediate shutdown trigger. PFSM Triggers There are various triggers that can enable a state transition between configured states. #GUID-B27AFE8A-2880-4705-9176-3CCD8F8C8AB9/T5973073-51 describes each trigger and its associated state transition from highest priority (Immediate Shutdown) to lowest priority. Active triggers of higher priority block triggers of lower priority and the associated sequence. State Transition Triggers Trigger Priority (ID) Immediate (IMM) REENTERANT PFSM Current State PFSM Destination State Power Sequence or Function Executed Immediate Shutdown 0 True False ANY TO_SAFE immediateOff2Safe_pd Orderly Shutdown 1 True False ANY TO_SAFE orderlyOff2safe 1 = High (Always True) 2 False False STANDBY LP STANDBY enterLPstandby FORCE_STANDBY 3 False False ACTIVE, STANDBY, S2R STANDBY orderlyOff WD_ERROR 4 False True ACTIVE ACTIVE warmReset ESM MCU Error 5 False True ACTIVE ACTIVE warmReset I2C_1 6 False True ACTIVE RUNTIME_BIST Execute RUNTIME BIST I2C_2 7 False True ACTIVE ACTIVE Enable I2C CRC on I 2C1 and I2C2 SU_ACTIVE 8 False False STANDBY ACTIVE any2active WKUP1 9 False False STANDBY, ACTIVE ACTIVE any2active I2C_0 10 False False ACTIVE STANDBY orderlyOff I2C_3 11 False False ACTIVE ACTIVE Device is prepared for OTA NVM update FORCE_STANDBY = LOW 12 False False PFSM_START ACTIVE any2active MCU_POWER_ERROR 13 False False ACTIVE ACTIVE warmReset GPIO9 (rise) 14 False True ACTIVE ACTIVE ENVPP GPIO9 (fall) 15 False True ACTIVE ACTIVE DISVPP GPIO5 (fall) 16 False True ACTIVE ACTIVE SD_1V8 GPIO5 (rise) 17 False True ACTIVE ACTIVE SD_3V3 GPIO11 (fall) 18 False True ACTIVE ACTIVE RST_SDCARD GPIO11 (rise) 19 False True ACTIVE ACTIVE EN_SDCARD A 20 False False ACTIVE, S2R ACTIVE any2active D 21 False False ACTIVE, S2R S2R any2_s2r 1 = High (Always True) 22 True False TO_SAFE SAFE_RECOVERY NA Power Sequences Sequence: immediateOff2Safe_pd The immediateOff2Safe_pd sequence occur when transition to the TO_SAFE state. The TPS65931211-Q1 PMIC immediately ceases BUCK switching and enables the pulldown resistors of the BUCKs and LDOs without delay. All rails are immediately shut down to prevent any damage of the PMICs in case of over voltage on VCCA or thermal shutdown. The timing is illustrated in . ImmediateOff Sequence Sequence: orderlyOff2safe If a moderate error occurs, an orderly shutdown trigger is generated. This trigger shuts down the PMIC outputs using the recommended power down sequence and proceed to the TO_SAFE state. If an OFF request occurs, such as the ENABLE pin of the TPS6593-Q1 device being pulled low, the same power down sequence occurs, except that the PMICs go to STANDBY (LP_STANDBY_SEL=0) or LP_STANDBY (LP_STANDBY_SEL=1) states, rather than going to the TO_SAFE state. The power sequence for both of these events is shown in . OrderlyOff Sequence Sequence: warmReset The warmReset sequence can be triggered by either a watchdog, ESM_MCU or MCU_POWER_ERROR. An output failure detection on LDO2 is a valid condition for the MCU_POWER_ERROR trigger which executes a warm reset. An output failure on any of the remaining power resources (Buck1/2/3/4/5 and LDO1/3/4) executes an orderly shutdown. In the event of a warm reset trigger, the nRSTOUT is driven low and the recovery count (register RECOV_CNT_REG_1) increments. Then, all BUCKs and LDOs are reset to their default voltages. The PMICs remain in the ACTIVE state. At the beginning of the sequence the following instructions are executed: \\ Mask LDO1 UV/OV REG_WRITE_MASK_IMM ADDR=0x04C DATA=0x03 MASK=0xFC \\ Set SPMI_LPM_EN REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x10 MASK=0xEF \\ Set LPM_EN and AMUXOUT_EN REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xEB // Increment the recovery counter REG_WRITE_MASK_IMM ADDR=0xa5 DATA=0x01 MASK=0xFE The watchdog or ESM error is an indication of a significant error which has taken place outside of the PMIC. The PMIC does not actually transition through the safe recovery, however, in order to maintain consistency all of the regulators are returned to the values stored in NVM and the recovery counter is incremented. If the recovery counter exceeds the recovery count threshold the PMICs stay in the safe recovery state. After the sequence, the MCU is responsible for managing the EN_DRV and recovery counter. At the end of the sequence the 'FORCE_EN_DRV_LOW' bit is cleared so that the MCU can set the ENABLE_DRV bit. Warm reset Sequence Sequence: any2active When a trigger causes the any2active sequence to execute, all Buck converters, LDO3 and LDO4 power up in the recommended power up sequence as shown in . LDO1 can be enabled with a rising edge on GPIO11 after nRSTOUT goes high. LDO2 can be enabled with a rising edge on GPIO9 after nRSTOUT goes high. At the beginning of the any2active sequence, the PMIC clear SPMI_LP_EN and LPM_EN and set AMUXOUT_EN and CLKMON_EN. any2active Sequence At the end of the any2active sequence the 'FORCE_EN_DRV_LOW' bit is cleared.After the any2active sequence the MCU is responsible for managing the EN_DRV. Sequence: any2_s2r The D and A triggers, defined by the NSLEEP2 bit or pin, trigger the any2_s2r sequence to support the IO+DDR low power mode on the processor. This sequence disables all power rails except Buck4 and Buck5 which supplies the 1.8V IO domain and DDR rails. The following PMIC PFSM instructions are executed automatically in the beginning and at the end of the power sequence://Instructions executed at the beginning of the sequence: //mask NSLEEP2 pin and NSLEEP2B bit REG_WRITE_MASK_IMM ADDR=0x07D DATA=0x80 MASK=0x7F // Instructions executed at the end of the sequence: // unmask NSLEEP2 pin and NSLEEP2B bit REG_WRITE_MASK_IMM ADDR=0x07D DATA=0x00 MASK=0x7F // set SPMI_LPM_EN REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x10 MASK=0xEF // Clear AMUXOUT_EN, CLKMON_EN, set LPM_EN REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xEB REG_WRITE_MASK_IMM ADDR=0x081 DATA=0x04 MASK=0xE3 Suspend to RAM Sequence Pre-Configurable Finite State Machine (PFSM) Settings This section describes the default PFSM settings of the TPS65931211-Q1 devices. These settings cannot be changed after device startup. This section describes the default PFSM settings of the TPS65931211-Q1 devices. These settings cannot be changed after device startup. This section describes the default PFSM settings of the TPS65931211-Q1 devices. These settings cannot be changed after device startup. Configured States In this PDN, the PMIC have the following configured power states: PFSM_START wait4Enable Active (Active SoC) S2R (IO + DDR) Standby (Partial IO, PMIC OFF) TO_SAFE shows the configured PDN power states along with the transition conditions to move between the states. Additionally, the transitions to hardware states, such as SAFE RECOVERY and LP_STANDBY are shown. The hardware states are part of the fixed device power Finite State Machine (FSM) and described in the TPS6593-Q1 data sheet, see . Pre-Configurable Finite State Machine (PFSM) Mission States and Transitions When the PMICs transition from the FSM to the PFSM, it waits for a valid ON Request before entering the ACTIVE state. The definition for each power state is described below: PFSM_START PFSM_START is the first state of the pre-configurable mission states. In this state the PMIC is powered by a valid supply. This state is entered when PMIC transitions from the FSM into PFSM. Once the PMIC arrives the PFSM_START, it waits for a valid ON request before transitioning to the next state. ACTIVE The PMIC is powered by a valid supply. The PMIC is fully functional and supply power to all PDN loads. The processor has completed a recommended power up sequence with all voltage domains energized. Refer to the sequence description. S2R The PMIC is powered by a valid supply. When the GPIO3 (nSLEEP2) is pulled low, only the power resources assigned to the 1.8V IO domain (Buck5) and the DDR (Buck4) are energized while all other domains are OFF to minimize total system power. EN_DRV is forced low in this state. This state supports the IO+DDR (suspend to RAM) low power mode on the AM62A. STANDBY The PMIC is powered by a valid supply on the system power rail (VCCA > VCCA_UV). All device resources are powered down in the STANDBY state. EN_DRV is forced low in this state. The processor is in the Off state, no voltage domains are energized. Refer to the sequence description. TO_SAFE If there is an event which causes MODERATE_ERR_INT = '1' or severe error from any of the previous described states, PMIC executes a orderly or immediate sequence and transitions out of the PFSM onto the FSM. MCU power errors and moderate errors result in the orderly shutdown trigger. Severe errors result in the immediate shutdown trigger. Configured States In this PDN, the PMIC have the following configured power states: PFSM_START wait4Enable Active (Active SoC) S2R (IO + DDR) Standby (Partial IO, PMIC OFF) TO_SAFE shows the configured PDN power states along with the transition conditions to move between the states. Additionally, the transitions to hardware states, such as SAFE RECOVERY and LP_STANDBY are shown. The hardware states are part of the fixed device power Finite State Machine (FSM) and described in the TPS6593-Q1 data sheet, see . Pre-Configurable Finite State Machine (PFSM) Mission States and Transitions When the PMICs transition from the FSM to the PFSM, it waits for a valid ON Request before entering the ACTIVE state. The definition for each power state is described below: PFSM_START PFSM_START is the first state of the pre-configurable mission states. In this state the PMIC is powered by a valid supply. This state is entered when PMIC transitions from the FSM into PFSM. Once the PMIC arrives the PFSM_START, it waits for a valid ON request before transitioning to the next state. ACTIVE The PMIC is powered by a valid supply. The PMIC is fully functional and supply power to all PDN loads. The processor has completed a recommended power up sequence with all voltage domains energized. Refer to the sequence description. S2R The PMIC is powered by a valid supply. When the GPIO3 (nSLEEP2) is pulled low, only the power resources assigned to the 1.8V IO domain (Buck5) and the DDR (Buck4) are energized while all other domains are OFF to minimize total system power. EN_DRV is forced low in this state. This state supports the IO+DDR (suspend to RAM) low power mode on the AM62A. STANDBY The PMIC is powered by a valid supply on the system power rail (VCCA > VCCA_UV). All device resources are powered down in the STANDBY state. EN_DRV is forced low in this state. The processor is in the Off state, no voltage domains are energized. Refer to the sequence description. TO_SAFE If there is an event which causes MODERATE_ERR_INT = '1' or severe error from any of the previous described states, PMIC executes a orderly or immediate sequence and transitions out of the PFSM onto the FSM. MCU power errors and moderate errors result in the orderly shutdown trigger. Severe errors result in the immediate shutdown trigger. In this PDN, the PMIC have the following configured power states: PFSM_START wait4Enable Active (Active SoC) S2R (IO + DDR) Standby (Partial IO, PMIC OFF) TO_SAFE shows the configured PDN power states along with the transition conditions to move between the states. Additionally, the transitions to hardware states, such as SAFE RECOVERY and LP_STANDBY are shown. The hardware states are part of the fixed device power Finite State Machine (FSM) and described in the TPS6593-Q1 data sheet, see . Pre-Configurable Finite State Machine (PFSM) Mission States and Transitions When the PMICs transition from the FSM to the PFSM, it waits for a valid ON Request before entering the ACTIVE state. The definition for each power state is described below: PFSM_START PFSM_START is the first state of the pre-configurable mission states. In this state the PMIC is powered by a valid supply. This state is entered when PMIC transitions from the FSM into PFSM. Once the PMIC arrives the PFSM_START, it waits for a valid ON request before transitioning to the next state. ACTIVE The PMIC is powered by a valid supply. The PMIC is fully functional and supply power to all PDN loads. The processor has completed a recommended power up sequence with all voltage domains energized. Refer to the sequence description. S2R The PMIC is powered by a valid supply. When the GPIO3 (nSLEEP2) is pulled low, only the power resources assigned to the 1.8V IO domain (Buck5) and the DDR (Buck4) are energized while all other domains are OFF to minimize total system power. EN_DRV is forced low in this state. This state supports the IO+DDR (suspend to RAM) low power mode on the AM62A. STANDBY The PMIC is powered by a valid supply on the system power rail (VCCA > VCCA_UV). All device resources are powered down in the STANDBY state. EN_DRV is forced low in this state. The processor is in the Off state, no voltage domains are energized. Refer to the sequence description. TO_SAFE If there is an event which causes MODERATE_ERR_INT = '1' or severe error from any of the previous described states, PMIC executes a orderly or immediate sequence and transitions out of the PFSM onto the FSM. MCU power errors and moderate errors result in the orderly shutdown trigger. Severe errors result in the immediate shutdown trigger. In this PDN, the PMIC have the following configured power states: PFSM_START wait4Enable Active (Active SoC) S2R (IO + DDR) Standby (Partial IO, PMIC OFF) TO_SAFE PFSM_STARTwait4EnableActive (Active SoC)S2R (IO + DDR)Standby (Partial IO, PMIC OFF)TO_SAFE shows the configured PDN power states along with the transition conditions to move between the states. Additionally, the transitions to hardware states, such as SAFE RECOVERY and LP_STANDBY are shown. The hardware states are part of the fixed device power Finite State Machine (FSM) and described in the TPS6593-Q1 data sheet, see . Pre-Configurable Finite State Machine (PFSM) Mission States and Transitions Pre-Configurable Finite State Machine (PFSM) Mission States and Transitions Pre-Configurable Finite State Machine (PFSM) Mission States and TransitionsWhen the PMICs transition from the FSM to the PFSM, it waits for a valid ON Request before entering the ACTIVE state. The definition for each power state is described below: PFSM_START PFSM_START is the first state of the pre-configurable mission states. In this state the PMIC is powered by a valid supply. This state is entered when PMIC transitions from the FSM into PFSM. Once the PMIC arrives the PFSM_START, it waits for a valid ON request before transitioning to the next state. ACTIVE The PMIC is powered by a valid supply. The PMIC is fully functional and supply power to all PDN loads. The processor has completed a recommended power up sequence with all voltage domains energized. Refer to the sequence description. S2R The PMIC is powered by a valid supply. When the GPIO3 (nSLEEP2) is pulled low, only the power resources assigned to the 1.8V IO domain (Buck5) and the DDR (Buck4) are energized while all other domains are OFF to minimize total system power. EN_DRV is forced low in this state. This state supports the IO+DDR (suspend to RAM) low power mode on the AM62A. STANDBY The PMIC is powered by a valid supply on the system power rail (VCCA > VCCA_UV). All device resources are powered down in the STANDBY state. EN_DRV is forced low in this state. The processor is in the Off state, no voltage domains are energized. Refer to the sequence description. TO_SAFE If there is an event which causes MODERATE_ERR_INT = '1' or severe error from any of the previous described states, PMIC executes a orderly or immediate sequence and transitions out of the PFSM onto the FSM. MCU power errors and moderate errors result in the orderly shutdown trigger. Severe errors result in the immediate shutdown trigger. PFSM_START PFSM_START is the first state of the pre-configurable mission states. In this state the PMIC is powered by a valid supply. This state is entered when PMIC transitions from the FSM into PFSM. Once the PMIC arrives the PFSM_START, it waits for a valid ON request before transitioning to the next state. PFSM_STARTPFSM_START is the first state of the pre-configurable mission states. In this state the PMIC is powered by a valid supply. This state is entered when PMIC transitions from the FSM into PFSM. Once the PMIC arrives the PFSM_START, it waits for a valid ON request before transitioning to the next state. ACTIVE The PMIC is powered by a valid supply. The PMIC is fully functional and supply power to all PDN loads. The processor has completed a recommended power up sequence with all voltage domains energized. Refer to the sequence description. ACTIVEThe PMIC is powered by a valid supply. The PMIC is fully functional and supply power to all PDN loads. The processor has completed a recommended power up sequence with all voltage domains energized. Refer to the sequence description. S2R The PMIC is powered by a valid supply. When the GPIO3 (nSLEEP2) is pulled low, only the power resources assigned to the 1.8V IO domain (Buck5) and the DDR (Buck4) are energized while all other domains are OFF to minimize total system power. EN_DRV is forced low in this state. This state supports the IO+DDR (suspend to RAM) low power mode on the AM62A. S2RThe PMIC is powered by a valid supply. When the GPIO3 (nSLEEP2) is pulled low, only the power resources assigned to the 1.8V IO domain (Buck5) and the DDR (Buck4) are energized while all other domains are OFF to minimize total system power. EN_DRV is forced low in this state. This state supports the IO+DDR (suspend to RAM) low power mode on the AM62A. STANDBY The PMIC is powered by a valid supply on the system power rail (VCCA > VCCA_UV). All device resources are powered down in the STANDBY state. EN_DRV is forced low in this state. The processor is in the Off state, no voltage domains are energized. Refer to the sequence description. STANDBYThe PMIC is powered by a valid supply on the system power rail (VCCA > VCCA_UV). All device resources are powered down in the STANDBY state. EN_DRV is forced low in this state. The processor is in the Off state, no voltage domains are energized. Refer to the sequence description. TO_SAFE If there is an event which causes MODERATE_ERR_INT = '1' or severe error from any of the previous described states, PMIC executes a orderly or immediate sequence and transitions out of the PFSM onto the FSM. MCU power errors and moderate errors result in the orderly shutdown trigger. Severe errors result in the immediate shutdown trigger. TO_SAFEIf there is an event which causes MODERATE_ERR_INT = '1' or severe error from any of the previous described states, PMIC executes a orderly or immediate sequence and transitions out of the PFSM onto the FSM. MCU power errors and moderate errors result in the orderly shutdown trigger. Severe errors result in the immediate shutdown trigger. PFSM Triggers There are various triggers that can enable a state transition between configured states. #GUID-B27AFE8A-2880-4705-9176-3CCD8F8C8AB9/T5973073-51 describes each trigger and its associated state transition from highest priority (Immediate Shutdown) to lowest priority. Active triggers of higher priority block triggers of lower priority and the associated sequence. State Transition Triggers Trigger Priority (ID) Immediate (IMM) REENTERANT PFSM Current State PFSM Destination State Power Sequence or Function Executed Immediate Shutdown 0 True False ANY TO_SAFE immediateOff2Safe_pd Orderly Shutdown 1 True False ANY TO_SAFE orderlyOff2safe 1 = High (Always True) 2 False False STANDBY LP STANDBY enterLPstandby FORCE_STANDBY 3 False False ACTIVE, STANDBY, S2R STANDBY orderlyOff WD_ERROR 4 False True ACTIVE ACTIVE warmReset ESM MCU Error 5 False True ACTIVE ACTIVE warmReset I2C_1 6 False True ACTIVE RUNTIME_BIST Execute RUNTIME BIST I2C_2 7 False True ACTIVE ACTIVE Enable I2C CRC on I 2C1 and I2C2 SU_ACTIVE 8 False False STANDBY ACTIVE any2active WKUP1 9 False False STANDBY, ACTIVE ACTIVE any2active I2C_0 10 False False ACTIVE STANDBY orderlyOff I2C_3 11 False False ACTIVE ACTIVE Device is prepared for OTA NVM update FORCE_STANDBY = LOW 12 False False PFSM_START ACTIVE any2active MCU_POWER_ERROR 13 False False ACTIVE ACTIVE warmReset GPIO9 (rise) 14 False True ACTIVE ACTIVE ENVPP GPIO9 (fall) 15 False True ACTIVE ACTIVE DISVPP GPIO5 (fall) 16 False True ACTIVE ACTIVE SD_1V8 GPIO5 (rise) 17 False True ACTIVE ACTIVE SD_3V3 GPIO11 (fall) 18 False True ACTIVE ACTIVE RST_SDCARD GPIO11 (rise) 19 False True ACTIVE ACTIVE EN_SDCARD A 20 False False ACTIVE, S2R ACTIVE any2active D 21 False False ACTIVE, S2R S2R any2_s2r 1 = High (Always True) 22 True False TO_SAFE SAFE_RECOVERY NA PFSM Triggers There are various triggers that can enable a state transition between configured states. #GUID-B27AFE8A-2880-4705-9176-3CCD8F8C8AB9/T5973073-51 describes each trigger and its associated state transition from highest priority (Immediate Shutdown) to lowest priority. Active triggers of higher priority block triggers of lower priority and the associated sequence. State Transition Triggers Trigger Priority (ID) Immediate (IMM) REENTERANT PFSM Current State PFSM Destination State Power Sequence or Function Executed Immediate Shutdown 0 True False ANY TO_SAFE immediateOff2Safe_pd Orderly Shutdown 1 True False ANY TO_SAFE orderlyOff2safe 1 = High (Always True) 2 False False STANDBY LP STANDBY enterLPstandby FORCE_STANDBY 3 False False ACTIVE, STANDBY, S2R STANDBY orderlyOff WD_ERROR 4 False True ACTIVE ACTIVE warmReset ESM MCU Error 5 False True ACTIVE ACTIVE warmReset I2C_1 6 False True ACTIVE RUNTIME_BIST Execute RUNTIME BIST I2C_2 7 False True ACTIVE ACTIVE Enable I2C CRC on I 2C1 and I2C2 SU_ACTIVE 8 False False STANDBY ACTIVE any2active WKUP1 9 False False STANDBY, ACTIVE ACTIVE any2active I2C_0 10 False False ACTIVE STANDBY orderlyOff I2C_3 11 False False ACTIVE ACTIVE Device is prepared for OTA NVM update FORCE_STANDBY = LOW 12 False False PFSM_START ACTIVE any2active MCU_POWER_ERROR 13 False False ACTIVE ACTIVE warmReset GPIO9 (rise) 14 False True ACTIVE ACTIVE ENVPP GPIO9 (fall) 15 False True ACTIVE ACTIVE DISVPP GPIO5 (fall) 16 False True ACTIVE ACTIVE SD_1V8 GPIO5 (rise) 17 False True ACTIVE ACTIVE SD_3V3 GPIO11 (fall) 18 False True ACTIVE ACTIVE RST_SDCARD GPIO11 (rise) 19 False True ACTIVE ACTIVE EN_SDCARD A 20 False False ACTIVE, S2R ACTIVE any2active D 21 False False ACTIVE, S2R S2R any2_s2r 1 = High (Always True) 22 True False TO_SAFE SAFE_RECOVERY NA There are various triggers that can enable a state transition between configured states. #GUID-B27AFE8A-2880-4705-9176-3CCD8F8C8AB9/T5973073-51 describes each trigger and its associated state transition from highest priority (Immediate Shutdown) to lowest priority. Active triggers of higher priority block triggers of lower priority and the associated sequence. State Transition Triggers Trigger Priority (ID) Immediate (IMM) REENTERANT PFSM Current State PFSM Destination State Power Sequence or Function Executed Immediate Shutdown 0 True False ANY TO_SAFE immediateOff2Safe_pd Orderly Shutdown 1 True False ANY TO_SAFE orderlyOff2safe 1 = High (Always True) 2 False False STANDBY LP STANDBY enterLPstandby FORCE_STANDBY 3 False False ACTIVE, STANDBY, S2R STANDBY orderlyOff WD_ERROR 4 False True ACTIVE ACTIVE warmReset ESM MCU Error 5 False True ACTIVE ACTIVE warmReset I2C_1 6 False True ACTIVE RUNTIME_BIST Execute RUNTIME BIST I2C_2 7 False True ACTIVE ACTIVE Enable I2C CRC on I 2C1 and I2C2 SU_ACTIVE 8 False False STANDBY ACTIVE any2active WKUP1 9 False False STANDBY, ACTIVE ACTIVE any2active I2C_0 10 False False ACTIVE STANDBY orderlyOff I2C_3 11 False False ACTIVE ACTIVE Device is prepared for OTA NVM update FORCE_STANDBY = LOW 12 False False PFSM_START ACTIVE any2active MCU_POWER_ERROR 13 False False ACTIVE ACTIVE warmReset GPIO9 (rise) 14 False True ACTIVE ACTIVE ENVPP GPIO9 (fall) 15 False True ACTIVE ACTIVE DISVPP GPIO5 (fall) 16 False True ACTIVE ACTIVE SD_1V8 GPIO5 (rise) 17 False True ACTIVE ACTIVE SD_3V3 GPIO11 (fall) 18 False True ACTIVE ACTIVE RST_SDCARD GPIO11 (rise) 19 False True ACTIVE ACTIVE EN_SDCARD A 20 False False ACTIVE, S2R ACTIVE any2active D 21 False False ACTIVE, S2R S2R any2_s2r 1 = High (Always True) 22 True False TO_SAFE SAFE_RECOVERY NA There are various triggers that can enable a state transition between configured states. #GUID-B27AFE8A-2880-4705-9176-3CCD8F8C8AB9/T5973073-51 describes each trigger and its associated state transition from highest priority (Immediate Shutdown) to lowest priority. Active triggers of higher priority block triggers of lower priority and the associated sequence. #GUID-B27AFE8A-2880-4705-9176-3CCD8F8C8AB9/T5973073-51 State Transition Triggers Trigger Priority (ID) Immediate (IMM) REENTERANT PFSM Current State PFSM Destination State Power Sequence or Function Executed Immediate Shutdown 0 True False ANY TO_SAFE immediateOff2Safe_pd Orderly Shutdown 1 True False ANY TO_SAFE orderlyOff2safe 1 = High (Always True) 2 False False STANDBY LP STANDBY enterLPstandby FORCE_STANDBY 3 False False ACTIVE, STANDBY, S2R STANDBY orderlyOff WD_ERROR 4 False True ACTIVE ACTIVE warmReset ESM MCU Error 5 False True ACTIVE ACTIVE warmReset I2C_1 6 False True ACTIVE RUNTIME_BIST Execute RUNTIME BIST I2C_2 7 False True ACTIVE ACTIVE Enable I2C CRC on I 2C1 and I2C2 SU_ACTIVE 8 False False STANDBY ACTIVE any2active WKUP1 9 False False STANDBY, ACTIVE ACTIVE any2active I2C_0 10 False False ACTIVE STANDBY orderlyOff I2C_3 11 False False ACTIVE ACTIVE Device is prepared for OTA NVM update FORCE_STANDBY = LOW 12 False False PFSM_START ACTIVE any2active MCU_POWER_ERROR 13 False False ACTIVE ACTIVE warmReset GPIO9 (rise) 14 False True ACTIVE ACTIVE ENVPP GPIO9 (fall) 15 False True ACTIVE ACTIVE DISVPP GPIO5 (fall) 16 False True ACTIVE ACTIVE SD_1V8 GPIO5 (rise) 17 False True ACTIVE ACTIVE SD_3V3 GPIO11 (fall) 18 False True ACTIVE ACTIVE RST_SDCARD GPIO11 (rise) 19 False True ACTIVE ACTIVE EN_SDCARD A 20 False False ACTIVE, S2R ACTIVE any2active D 21 False False ACTIVE, S2R S2R any2_s2r 1 = High (Always True) 22 True False TO_SAFE SAFE_RECOVERY NA State Transition Triggers Trigger Priority (ID) Immediate (IMM) REENTERANT PFSM Current State PFSM Destination State Power Sequence or Function Executed Immediate Shutdown 0 True False ANY TO_SAFE immediateOff2Safe_pd Orderly Shutdown 1 True False ANY TO_SAFE orderlyOff2safe 1 = High (Always True) 2 False False STANDBY LP STANDBY enterLPstandby FORCE_STANDBY 3 False False ACTIVE, STANDBY, S2R STANDBY orderlyOff WD_ERROR 4 False True ACTIVE ACTIVE warmReset ESM MCU Error 5 False True ACTIVE ACTIVE warmReset I2C_1 6 False True ACTIVE RUNTIME_BIST Execute RUNTIME BIST I2C_2 7 False True ACTIVE ACTIVE Enable I2C CRC on I 2C1 and I2C2 SU_ACTIVE 8 False False STANDBY ACTIVE any2active WKUP1 9 False False STANDBY, ACTIVE ACTIVE any2active I2C_0 10 False False ACTIVE STANDBY orderlyOff I2C_3 11 False False ACTIVE ACTIVE Device is prepared for OTA NVM update FORCE_STANDBY = LOW 12 False False PFSM_START ACTIVE any2active MCU_POWER_ERROR 13 False False ACTIVE ACTIVE warmReset GPIO9 (rise) 14 False True ACTIVE ACTIVE ENVPP GPIO9 (fall) 15 False True ACTIVE ACTIVE DISVPP GPIO5 (fall) 16 False True ACTIVE ACTIVE SD_1V8 GPIO5 (rise) 17 False True ACTIVE ACTIVE SD_3V3 GPIO11 (fall) 18 False True ACTIVE ACTIVE RST_SDCARD GPIO11 (rise) 19 False True ACTIVE ACTIVE EN_SDCARD A 20 False False ACTIVE, S2R ACTIVE any2active D 21 False False ACTIVE, S2R S2R any2_s2r 1 = High (Always True) 22 True False TO_SAFE SAFE_RECOVERY NA Trigger Priority (ID) Immediate (IMM) REENTERANT PFSM Current State PFSM Destination State Power Sequence or Function Executed Trigger Priority (ID) Immediate (IMM) REENTERANT PFSM Current State PFSM Destination State Power Sequence or Function Executed TriggerPriority (ID)Immediate (IMM)REENTERANTPFSM Current StatePFSM Destination StatePower Sequence or Function Executed Immediate Shutdown 0 True False ANY TO_SAFE immediateOff2Safe_pd Orderly Shutdown 1 True False ANY TO_SAFE orderlyOff2safe 1 = High (Always True) 2 False False STANDBY LP STANDBY enterLPstandby FORCE_STANDBY 3 False False ACTIVE, STANDBY, S2R STANDBY orderlyOff WD_ERROR 4 False True ACTIVE ACTIVE warmReset ESM MCU Error 5 False True ACTIVE ACTIVE warmReset I2C_1 6 False True ACTIVE RUNTIME_BIST Execute RUNTIME BIST I2C_2 7 False True ACTIVE ACTIVE Enable I2C CRC on I 2C1 and I2C2 SU_ACTIVE 8 False False STANDBY ACTIVE any2active WKUP1 9 False False STANDBY, ACTIVE ACTIVE any2active I2C_0 10 False False ACTIVE STANDBY orderlyOff I2C_3 11 False False ACTIVE ACTIVE Device is prepared for OTA NVM update FORCE_STANDBY = LOW 12 False False PFSM_START ACTIVE any2active MCU_POWER_ERROR 13 False False ACTIVE ACTIVE warmReset GPIO9 (rise) 14 False True ACTIVE ACTIVE ENVPP GPIO9 (fall) 15 False True ACTIVE ACTIVE DISVPP GPIO5 (fall) 16 False True ACTIVE ACTIVE SD_1V8 GPIO5 (rise) 17 False True ACTIVE ACTIVE SD_3V3 GPIO11 (fall) 18 False True ACTIVE ACTIVE RST_SDCARD GPIO11 (rise) 19 False True ACTIVE ACTIVE EN_SDCARD A 20 False False ACTIVE, S2R ACTIVE any2active D 21 False False ACTIVE, S2R S2R any2_s2r 1 = High (Always True) 22 True False TO_SAFE SAFE_RECOVERY NA Immediate Shutdown 0 True False ANY TO_SAFE immediateOff2Safe_pd Immediate Shutdown0TrueFalseANYTO_SAFEimmediateOff2Safe_pd Orderly Shutdown 1 True False ANY TO_SAFE orderlyOff2safe Orderly Shutdown1TrueFalseANYTO_SAFEorderlyOff2safe 1 = High (Always True) 2 False False STANDBY LP STANDBY enterLPstandby 1 = High (Always True)2FalseFalseSTANDBYLP STANDBYenterLPstandby FORCE_STANDBY 3 False False ACTIVE, STANDBY, S2R STANDBY orderlyOff FORCE_STANDBY 3FalseFalseACTIVE, STANDBY, S2RSTANDBYorderlyOff WD_ERROR 4 False True ACTIVE ACTIVE warmReset WD_ERROR4FalseTrueACTIVEACTIVEwarmReset ESM MCU Error 5 False True ACTIVE ACTIVE warmReset ESM MCU Error5FalseTrueACTIVEACTIVEwarmReset I2C_1 6 False True ACTIVE RUNTIME_BIST Execute RUNTIME BIST I2C_16FalseTrueACTIVERUNTIME_BISTExecute RUNTIME BIST I2C_2 7 False True ACTIVE ACTIVE Enable I2C CRC on I 2C1 and I2C2 I2C_27FalseTrueACTIVEACTIVEEnable I2C CRC on I 2C1 and I2C2 SU_ACTIVE 8 False False STANDBY ACTIVE any2active SU_ACTIVE8FalseFalseSTANDBYACTIVEany2active WKUP1 9 False False STANDBY, ACTIVE ACTIVE any2active WKUP19FalseFalseSTANDBY, ACTIVEACTIVEany2active I2C_0 10 False False ACTIVE STANDBY orderlyOff I2C_010FalseFalseACTIVESTANDBYorderlyOff I2C_3 11 False False ACTIVE ACTIVE Device is prepared for OTA NVM update I2C_311FalseFalseACTIVEACTIVEDevice is prepared for OTA NVM update FORCE_STANDBY = LOW 12 False False PFSM_START ACTIVE any2active FORCE_STANDBY = LOW12FalseFalsePFSM_STARTACTIVEany2active MCU_POWER_ERROR 13 False False ACTIVE ACTIVE warmReset MCU_POWER_ERROR13FalseFalseACTIVEACTIVEwarmReset GPIO9 (rise) 14 False True ACTIVE ACTIVE ENVPP GPIO9 (rise)14FalseTrueACTIVEACTIVEENVPP GPIO9 (fall) 15 False True ACTIVE ACTIVE DISVPP GPIO9 (fall)15FalseTrueACTIVEACTIVEDISVPP GPIO5 (fall) 16 False True ACTIVE ACTIVE SD_1V8 GPIO5 (fall)16FalseTrueACTIVEACTIVESD_1V8 GPIO5 (rise) 17 False True ACTIVE ACTIVE SD_3V3 GPIO5 (rise)17FalseTrueACTIVEACTIVESD_3V3 GPIO11 (fall) 18 False True ACTIVE ACTIVE RST_SDCARD GPIO11 (fall)18FalseTrueACTIVEACTIVERST_SDCARD GPIO11 (rise) 19 False True ACTIVE ACTIVE EN_SDCARD GPIO11 (rise)19FalseTrueACTIVEACTIVEEN_SDCARD A 20 False False ACTIVE, S2R ACTIVE any2active A20FalseFalseACTIVE, S2RACTIVEany2active D 21 False False ACTIVE, S2R S2R any2_s2r D21FalseFalseACTIVE, S2RS2Rany2_s2r 1 = High (Always True) 22 True False TO_SAFE SAFE_RECOVERY NA 1 = High (Always True)22TrueFalseTO_SAFESAFE_RECOVERYNA Power Sequences Sequence: immediateOff2Safe_pd The immediateOff2Safe_pd sequence occur when transition to the TO_SAFE state. The TPS65931211-Q1 PMIC immediately ceases BUCK switching and enables the pulldown resistors of the BUCKs and LDOs without delay. All rails are immediately shut down to prevent any damage of the PMICs in case of over voltage on VCCA or thermal shutdown. The timing is illustrated in . ImmediateOff Sequence Sequence: orderlyOff2safe If a moderate error occurs, an orderly shutdown trigger is generated. This trigger shuts down the PMIC outputs using the recommended power down sequence and proceed to the TO_SAFE state. If an OFF request occurs, such as the ENABLE pin of the TPS6593-Q1 device being pulled low, the same power down sequence occurs, except that the PMICs go to STANDBY (LP_STANDBY_SEL=0) or LP_STANDBY (LP_STANDBY_SEL=1) states, rather than going to the TO_SAFE state. The power sequence for both of these events is shown in . OrderlyOff Sequence Sequence: warmReset The warmReset sequence can be triggered by either a watchdog, ESM_MCU or MCU_POWER_ERROR. An output failure detection on LDO2 is a valid condition for the MCU_POWER_ERROR trigger which executes a warm reset. An output failure on any of the remaining power resources (Buck1/2/3/4/5 and LDO1/3/4) executes an orderly shutdown. In the event of a warm reset trigger, the nRSTOUT is driven low and the recovery count (register RECOV_CNT_REG_1) increments. Then, all BUCKs and LDOs are reset to their default voltages. The PMICs remain in the ACTIVE state. At the beginning of the sequence the following instructions are executed: \\ Mask LDO1 UV/OV REG_WRITE_MASK_IMM ADDR=0x04C DATA=0x03 MASK=0xFC \\ Set SPMI_LPM_EN REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x10 MASK=0xEF \\ Set LPM_EN and AMUXOUT_EN REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xEB // Increment the recovery counter REG_WRITE_MASK_IMM ADDR=0xa5 DATA=0x01 MASK=0xFE The watchdog or ESM error is an indication of a significant error which has taken place outside of the PMIC. The PMIC does not actually transition through the safe recovery, however, in order to maintain consistency all of the regulators are returned to the values stored in NVM and the recovery counter is incremented. If the recovery counter exceeds the recovery count threshold the PMICs stay in the safe recovery state. After the sequence, the MCU is responsible for managing the EN_DRV and recovery counter. At the end of the sequence the 'FORCE_EN_DRV_LOW' bit is cleared so that the MCU can set the ENABLE_DRV bit. Warm reset Sequence Sequence: any2active When a trigger causes the any2active sequence to execute, all Buck converters, LDO3 and LDO4 power up in the recommended power up sequence as shown in . LDO1 can be enabled with a rising edge on GPIO11 after nRSTOUT goes high. LDO2 can be enabled with a rising edge on GPIO9 after nRSTOUT goes high. At the beginning of the any2active sequence, the PMIC clear SPMI_LP_EN and LPM_EN and set AMUXOUT_EN and CLKMON_EN. any2active Sequence At the end of the any2active sequence the 'FORCE_EN_DRV_LOW' bit is cleared.After the any2active sequence the MCU is responsible for managing the EN_DRV. Sequence: any2_s2r The D and A triggers, defined by the NSLEEP2 bit or pin, trigger the any2_s2r sequence to support the IO+DDR low power mode on the processor. This sequence disables all power rails except Buck4 and Buck5 which supplies the 1.8V IO domain and DDR rails. The following PMIC PFSM instructions are executed automatically in the beginning and at the end of the power sequence://Instructions executed at the beginning of the sequence: //mask NSLEEP2 pin and NSLEEP2B bit REG_WRITE_MASK_IMM ADDR=0x07D DATA=0x80 MASK=0x7F // Instructions executed at the end of the sequence: // unmask NSLEEP2 pin and NSLEEP2B bit REG_WRITE_MASK_IMM ADDR=0x07D DATA=0x00 MASK=0x7F // set SPMI_LPM_EN REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x10 MASK=0xEF // Clear AMUXOUT_EN, CLKMON_EN, set LPM_EN REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xEB REG_WRITE_MASK_IMM ADDR=0x081 DATA=0x04 MASK=0xE3 Suspend to RAM Sequence Power Sequences Sequence: immediateOff2Safe_pd The immediateOff2Safe_pd sequence occur when transition to the TO_SAFE state. The TPS65931211-Q1 PMIC immediately ceases BUCK switching and enables the pulldown resistors of the BUCKs and LDOs without delay. All rails are immediately shut down to prevent any damage of the PMICs in case of over voltage on VCCA or thermal shutdown. The timing is illustrated in . ImmediateOff Sequence Sequence: immediateOff2Safe_pd The immediateOff2Safe_pd sequence occur when transition to the TO_SAFE state. The TPS65931211-Q1 PMIC immediately ceases BUCK switching and enables the pulldown resistors of the BUCKs and LDOs without delay. All rails are immediately shut down to prevent any damage of the PMICs in case of over voltage on VCCA or thermal shutdown. The timing is illustrated in . ImmediateOff Sequence The immediateOff2Safe_pd sequence occur when transition to the TO_SAFE state. The TPS65931211-Q1 PMIC immediately ceases BUCK switching and enables the pulldown resistors of the BUCKs and LDOs without delay. All rails are immediately shut down to prevent any damage of the PMICs in case of over voltage on VCCA or thermal shutdown. The timing is illustrated in . ImmediateOff Sequence The immediateOff2Safe_pd sequence occur when transition to the TO_SAFE state. The TPS65931211-Q1 PMIC immediately ceases BUCK switching and enables the pulldown resistors of the BUCKs and LDOs without delay. All rails are immediately shut down to prevent any damage of the PMICs in case of over voltage on VCCA or thermal shutdown. The timing is illustrated in . ImmediateOff Sequence ImmediateOff Sequence ImmediateOff Sequence Sequence: orderlyOff2safe If a moderate error occurs, an orderly shutdown trigger is generated. This trigger shuts down the PMIC outputs using the recommended power down sequence and proceed to the TO_SAFE state. If an OFF request occurs, such as the ENABLE pin of the TPS6593-Q1 device being pulled low, the same power down sequence occurs, except that the PMICs go to STANDBY (LP_STANDBY_SEL=0) or LP_STANDBY (LP_STANDBY_SEL=1) states, rather than going to the TO_SAFE state. The power sequence for both of these events is shown in . OrderlyOff Sequence Sequence: orderlyOff2safe If a moderate error occurs, an orderly shutdown trigger is generated. This trigger shuts down the PMIC outputs using the recommended power down sequence and proceed to the TO_SAFE state. If an OFF request occurs, such as the ENABLE pin of the TPS6593-Q1 device being pulled low, the same power down sequence occurs, except that the PMICs go to STANDBY (LP_STANDBY_SEL=0) or LP_STANDBY (LP_STANDBY_SEL=1) states, rather than going to the TO_SAFE state. The power sequence for both of these events is shown in . OrderlyOff Sequence If a moderate error occurs, an orderly shutdown trigger is generated. This trigger shuts down the PMIC outputs using the recommended power down sequence and proceed to the TO_SAFE state. If an OFF request occurs, such as the ENABLE pin of the TPS6593-Q1 device being pulled low, the same power down sequence occurs, except that the PMICs go to STANDBY (LP_STANDBY_SEL=0) or LP_STANDBY (LP_STANDBY_SEL=1) states, rather than going to the TO_SAFE state. The power sequence for both of these events is shown in . OrderlyOff Sequence If a moderate error occurs, an orderly shutdown trigger is generated. This trigger shuts down the PMIC outputs using the recommended power down sequence and proceed to the TO_SAFE state.If an OFF request occurs, such as the ENABLE pin of the TPS6593-Q1 device being pulled low, the same power down sequence occurs, except that the PMICs go to STANDBY (LP_STANDBY_SEL=0) or LP_STANDBY (LP_STANDBY_SEL=1) states, rather than going to the TO_SAFE state. The power sequence for both of these events is shown in . OrderlyOff Sequence OrderlyOff Sequence OrderlyOff Sequence Sequence: warmReset The warmReset sequence can be triggered by either a watchdog, ESM_MCU or MCU_POWER_ERROR. An output failure detection on LDO2 is a valid condition for the MCU_POWER_ERROR trigger which executes a warm reset. An output failure on any of the remaining power resources (Buck1/2/3/4/5 and LDO1/3/4) executes an orderly shutdown. In the event of a warm reset trigger, the nRSTOUT is driven low and the recovery count (register RECOV_CNT_REG_1) increments. Then, all BUCKs and LDOs are reset to their default voltages. The PMICs remain in the ACTIVE state. At the beginning of the sequence the following instructions are executed: \\ Mask LDO1 UV/OV REG_WRITE_MASK_IMM ADDR=0x04C DATA=0x03 MASK=0xFC \\ Set SPMI_LPM_EN REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x10 MASK=0xEF \\ Set LPM_EN and AMUXOUT_EN REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xEB // Increment the recovery counter REG_WRITE_MASK_IMM ADDR=0xa5 DATA=0x01 MASK=0xFE The watchdog or ESM error is an indication of a significant error which has taken place outside of the PMIC. The PMIC does not actually transition through the safe recovery, however, in order to maintain consistency all of the regulators are returned to the values stored in NVM and the recovery counter is incremented. If the recovery counter exceeds the recovery count threshold the PMICs stay in the safe recovery state. After the sequence, the MCU is responsible for managing the EN_DRV and recovery counter. At the end of the sequence the 'FORCE_EN_DRV_LOW' bit is cleared so that the MCU can set the ENABLE_DRV bit. Warm reset Sequence Sequence: warmReset The warmReset sequence can be triggered by either a watchdog, ESM_MCU or MCU_POWER_ERROR. An output failure detection on LDO2 is a valid condition for the MCU_POWER_ERROR trigger which executes a warm reset. An output failure on any of the remaining power resources (Buck1/2/3/4/5 and LDO1/3/4) executes an orderly shutdown. In the event of a warm reset trigger, the nRSTOUT is driven low and the recovery count (register RECOV_CNT_REG_1) increments. Then, all BUCKs and LDOs are reset to their default voltages. The PMICs remain in the ACTIVE state. At the beginning of the sequence the following instructions are executed: \\ Mask LDO1 UV/OV REG_WRITE_MASK_IMM ADDR=0x04C DATA=0x03 MASK=0xFC \\ Set SPMI_LPM_EN REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x10 MASK=0xEF \\ Set LPM_EN and AMUXOUT_EN REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xEB // Increment the recovery counter REG_WRITE_MASK_IMM ADDR=0xa5 DATA=0x01 MASK=0xFE The watchdog or ESM error is an indication of a significant error which has taken place outside of the PMIC. The PMIC does not actually transition through the safe recovery, however, in order to maintain consistency all of the regulators are returned to the values stored in NVM and the recovery counter is incremented. If the recovery counter exceeds the recovery count threshold the PMICs stay in the safe recovery state. After the sequence, the MCU is responsible for managing the EN_DRV and recovery counter. At the end of the sequence the 'FORCE_EN_DRV_LOW' bit is cleared so that the MCU can set the ENABLE_DRV bit. Warm reset Sequence The warmReset sequence can be triggered by either a watchdog, ESM_MCU or MCU_POWER_ERROR. An output failure detection on LDO2 is a valid condition for the MCU_POWER_ERROR trigger which executes a warm reset. An output failure on any of the remaining power resources (Buck1/2/3/4/5 and LDO1/3/4) executes an orderly shutdown. In the event of a warm reset trigger, the nRSTOUT is driven low and the recovery count (register RECOV_CNT_REG_1) increments. Then, all BUCKs and LDOs are reset to their default voltages. The PMICs remain in the ACTIVE state. At the beginning of the sequence the following instructions are executed: \\ Mask LDO1 UV/OV REG_WRITE_MASK_IMM ADDR=0x04C DATA=0x03 MASK=0xFC \\ Set SPMI_LPM_EN REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x10 MASK=0xEF \\ Set LPM_EN and AMUXOUT_EN REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xEB // Increment the recovery counter REG_WRITE_MASK_IMM ADDR=0xa5 DATA=0x01 MASK=0xFE The watchdog or ESM error is an indication of a significant error which has taken place outside of the PMIC. The PMIC does not actually transition through the safe recovery, however, in order to maintain consistency all of the regulators are returned to the values stored in NVM and the recovery counter is incremented. If the recovery counter exceeds the recovery count threshold the PMICs stay in the safe recovery state. After the sequence, the MCU is responsible for managing the EN_DRV and recovery counter. At the end of the sequence the 'FORCE_EN_DRV_LOW' bit is cleared so that the MCU can set the ENABLE_DRV bit. Warm reset Sequence The warmReset sequence can be triggered by either a watchdog, ESM_MCU or MCU_POWER_ERROR. An output failure detection on LDO2 is a valid condition for the MCU_POWER_ERROR trigger which executes a warm reset. An output failure on any of the remaining power resources (Buck1/2/3/4/5 and LDO1/3/4) executes an orderly shutdown. In the event of a warm reset trigger, the nRSTOUT is driven low and the recovery count (register RECOV_CNT_REG_1) increments. Then, all BUCKs and LDOs are reset to their default voltages. The PMICs remain in the ACTIVE state.At the beginning of the sequence the following instructions are executed: \\ Mask LDO1 UV/OV REG_WRITE_MASK_IMM ADDR=0x04C DATA=0x03 MASK=0xFC \\ Set SPMI_LPM_EN REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x10 MASK=0xEF \\ Set LPM_EN and AMUXOUT_EN REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xEB // Increment the recovery counter REG_WRITE_MASK_IMM ADDR=0xa5 DATA=0x01 MASK=0xFE The watchdog or ESM error is an indication of a significant error which has taken place outside of the PMIC. The PMIC does not actually transition through the safe recovery, however, in order to maintain consistency all of the regulators are returned to the values stored in NVM and the recovery counter is incremented. If the recovery counter exceeds the recovery count threshold the PMICs stay in the safe recovery state. After the sequence, the MCU is responsible for managing the EN_DRV and recovery counter. At the end of the sequence the 'FORCE_EN_DRV_LOW' bit is cleared so that the MCU can set the ENABLE_DRV bit. \\ Mask LDO1 UV/OV REG_WRITE_MASK_IMM ADDR=0x04C DATA=0x03 MASK=0xFC \\ Set SPMI_LPM_EN REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x10 MASK=0xEF \\ Set LPM_EN and AMUXOUT_EN REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xEB // Increment the recovery counter REG_WRITE_MASK_IMM ADDR=0xa5 DATA=0x01 MASK=0xFEThe watchdog or ESM error is an indication of a significant error which has taken place outside of the PMIC. The PMIC does not actually transition through the safe recovery, however, in order to maintain consistency all of the regulators are returned to the values stored in NVM and the recovery counter is incremented. If the recovery counter exceeds the recovery count threshold the PMICs stay in the safe recovery state. After the sequence, the MCU is responsible for managing the EN_DRV and recovery counter. At the end of the sequence the 'FORCE_EN_DRV_LOW' bit is cleared so that the MCU can set the ENABLE_DRV bit. Warm reset Sequence Warm reset Sequence Warm reset Sequence Sequence: any2active When a trigger causes the any2active sequence to execute, all Buck converters, LDO3 and LDO4 power up in the recommended power up sequence as shown in . LDO1 can be enabled with a rising edge on GPIO11 after nRSTOUT goes high. LDO2 can be enabled with a rising edge on GPIO9 after nRSTOUT goes high. At the beginning of the any2active sequence, the PMIC clear SPMI_LP_EN and LPM_EN and set AMUXOUT_EN and CLKMON_EN. any2active Sequence At the end of the any2active sequence the 'FORCE_EN_DRV_LOW' bit is cleared.After the any2active sequence the MCU is responsible for managing the EN_DRV. Sequence: any2active When a trigger causes the any2active sequence to execute, all Buck converters, LDO3 and LDO4 power up in the recommended power up sequence as shown in . LDO1 can be enabled with a rising edge on GPIO11 after nRSTOUT goes high. LDO2 can be enabled with a rising edge on GPIO9 after nRSTOUT goes high. At the beginning of the any2active sequence, the PMIC clear SPMI_LP_EN and LPM_EN and set AMUXOUT_EN and CLKMON_EN. any2active Sequence At the end of the any2active sequence the 'FORCE_EN_DRV_LOW' bit is cleared.After the any2active sequence the MCU is responsible for managing the EN_DRV. When a trigger causes the any2active sequence to execute, all Buck converters, LDO3 and LDO4 power up in the recommended power up sequence as shown in . LDO1 can be enabled with a rising edge on GPIO11 after nRSTOUT goes high. LDO2 can be enabled with a rising edge on GPIO9 after nRSTOUT goes high. At the beginning of the any2active sequence, the PMIC clear SPMI_LP_EN and LPM_EN and set AMUXOUT_EN and CLKMON_EN. any2active Sequence At the end of the any2active sequence the 'FORCE_EN_DRV_LOW' bit is cleared.After the any2active sequence the MCU is responsible for managing the EN_DRV. When a trigger causes the any2active sequence to execute, all Buck converters, LDO3 and LDO4 power up in the recommended power up sequence as shown in . LDO1 can be enabled with a rising edge on GPIO11 after nRSTOUT goes high. LDO2 can be enabled with a rising edge on GPIO9 after nRSTOUT goes high. At the beginning of the any2active sequence, the PMIC clear SPMI_LP_EN and LPM_EN and set AMUXOUT_EN and CLKMON_EN. any2active Sequence any2active Sequence any2active SequenceAt the end of the any2active sequence the 'FORCE_EN_DRV_LOW' bit is cleared.After the any2active sequence the MCU is responsible for managing the EN_DRV. After the any2active sequence the MCU is responsible for managing the EN_DRV. Sequence: any2_s2r The D and A triggers, defined by the NSLEEP2 bit or pin, trigger the any2_s2r sequence to support the IO+DDR low power mode on the processor. This sequence disables all power rails except Buck4 and Buck5 which supplies the 1.8V IO domain and DDR rails. The following PMIC PFSM instructions are executed automatically in the beginning and at the end of the power sequence://Instructions executed at the beginning of the sequence: //mask NSLEEP2 pin and NSLEEP2B bit REG_WRITE_MASK_IMM ADDR=0x07D DATA=0x80 MASK=0x7F // Instructions executed at the end of the sequence: // unmask NSLEEP2 pin and NSLEEP2B bit REG_WRITE_MASK_IMM ADDR=0x07D DATA=0x00 MASK=0x7F // set SPMI_LPM_EN REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x10 MASK=0xEF // Clear AMUXOUT_EN, CLKMON_EN, set LPM_EN REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xEB REG_WRITE_MASK_IMM ADDR=0x081 DATA=0x04 MASK=0xE3 Suspend to RAM Sequence Sequence: any2_s2r The D and A triggers, defined by the NSLEEP2 bit or pin, trigger the any2_s2r sequence to support the IO+DDR low power mode on the processor. This sequence disables all power rails except Buck4 and Buck5 which supplies the 1.8V IO domain and DDR rails. The following PMIC PFSM instructions are executed automatically in the beginning and at the end of the power sequence://Instructions executed at the beginning of the sequence: //mask NSLEEP2 pin and NSLEEP2B bit REG_WRITE_MASK_IMM ADDR=0x07D DATA=0x80 MASK=0x7F // Instructions executed at the end of the sequence: // unmask NSLEEP2 pin and NSLEEP2B bit REG_WRITE_MASK_IMM ADDR=0x07D DATA=0x00 MASK=0x7F // set SPMI_LPM_EN REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x10 MASK=0xEF // Clear AMUXOUT_EN, CLKMON_EN, set LPM_EN REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xEB REG_WRITE_MASK_IMM ADDR=0x081 DATA=0x04 MASK=0xE3 Suspend to RAM Sequence The D and A triggers, defined by the NSLEEP2 bit or pin, trigger the any2_s2r sequence to support the IO+DDR low power mode on the processor. This sequence disables all power rails except Buck4 and Buck5 which supplies the 1.8V IO domain and DDR rails. The following PMIC PFSM instructions are executed automatically in the beginning and at the end of the power sequence://Instructions executed at the beginning of the sequence: //mask NSLEEP2 pin and NSLEEP2B bit REG_WRITE_MASK_IMM ADDR=0x07D DATA=0x80 MASK=0x7F // Instructions executed at the end of the sequence: // unmask NSLEEP2 pin and NSLEEP2B bit REG_WRITE_MASK_IMM ADDR=0x07D DATA=0x00 MASK=0x7F // set SPMI_LPM_EN REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x10 MASK=0xEF // Clear AMUXOUT_EN, CLKMON_EN, set LPM_EN REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xEB REG_WRITE_MASK_IMM ADDR=0x081 DATA=0x04 MASK=0xE3 Suspend to RAM Sequence The D and A triggers, defined by the NSLEEP2 bit or pin, trigger the any2_s2r sequence to support the IO+DDR low power mode on the processor. This sequence disables all power rails except Buck4 and Buck5 which supplies the 1.8V IO domain and DDR rails. The following PMIC PFSM instructions are executed automatically in the beginning and at the end of the power sequence://Instructions executed at the beginning of the sequence: //mask NSLEEP2 pin and NSLEEP2B bit REG_WRITE_MASK_IMM ADDR=0x07D DATA=0x80 MASK=0x7F // Instructions executed at the end of the sequence: // unmask NSLEEP2 pin and NSLEEP2B bit REG_WRITE_MASK_IMM ADDR=0x07D DATA=0x00 MASK=0x7F // set SPMI_LPM_EN REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x10 MASK=0xEF // Clear AMUXOUT_EN, CLKMON_EN, set LPM_EN REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xEB REG_WRITE_MASK_IMM ADDR=0x081 DATA=0x04 MASK=0xE3 //Instructions executed at the beginning of the sequence: //mask NSLEEP2 pin and NSLEEP2B bit REG_WRITE_MASK_IMM ADDR=0x07D DATA=0x80 MASK=0x7F// Instructions executed at the end of the sequence: // unmask NSLEEP2 pin and NSLEEP2B bit REG_WRITE_MASK_IMM ADDR=0x07D DATA=0x00 MASK=0x7F // set SPMI_LPM_EN REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x10 MASK=0xEF // Clear AMUXOUT_EN, CLKMON_EN, set LPM_EN REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xEB REG_WRITE_MASK_IMM ADDR=0x081 DATA=0x04 MASK=0xE3 Suspend to RAM Sequence Suspend to RAM Sequence Suspend to RAM Sequence Application Examples This section provides examples of how to interact with the PMICs from the perspective of the MCU and over I2C. #GUID-D5C06820-6F5D-429A-B389-914AFCC7F5EA/GUID-D13CC848-0A7B-45ED-BFB8-0F5A5B93761C shows how the I2C commands are presented in the following sections. These examples, when used in conjunction with the data sheet, can be generalized and applied to other use cases. I²C Instruction Format I2C Address Register Address Data Mask 0x48 or 0x4C 0x00 - 0xFF 0x00 - 0xFF 0x00 - 0xFF Entering and Exiting S2R (Suspend to RAM) The default configuration of the NVM transitions the PMICs to the ACTIVE state when the ENABLE pin on the TPS65931211 goes high. The nINT pin goes low to indicate that an interrupt has occurred in the PMICs. After a normal power up sequence the BIST_PASS_INT field in the INT_MISC register is set. This interrupt bit indicates that BIST has been completed. Once the BIST_PASS_INT is cleared, the nINT pin is released (goes high) and PMIC can transition to a different state like S2R or Standby. The following section describe how to enter and exit the S2R state by hardware (using the GPIO3 pin) or by software (writing to the NSLEEP2B bit). State Table NSLEEP2(GPIO3) NSLEEP2B(register field) NSLEEP1B(register field) NSLEEP1_MASK(register field) NSLEEP2_MASK(register field) State / Trigger High Don't care Don't care 1 0 ACTIVE State /Trigger A Low 1 Don't care 1 0 ACTIVE State /Trigger A Low 0 Don't care 1 0 S2R State / Trigger D The NSLEEP1_MASK bit on register CONFIG_1 is set by default so the NSLEEP1 trigger does not affect FSM state transition. The mask settings can be changed by I2C when the PMIC is in Active state. The following code block shows how to execute triggers A and D using I2C commands to transition in and out of the S2R state. In this example the, PMIC is already in the S2R state after the GPIO3 was pulled low. The NSLEEP2B register field has effect only if GPO3 (NSLEEP2) is low. Write 0x48:0x86:0x01:0xFE // Set NSLEEP2B to transition out of the S2R state (Trigger A) Write 0x48:0x86:0x00:0xFE // Clear NSLEEP2B to trigger "any2_s2r" sequence (Trigger D) Instead of writing to the NSLEEP2B bit to return to the ACTIVE state, it is also possible to use the GPIO3 pin to return the PMIC to the ACTIVE state. Entering and Exiting Standby STANDBY can be entered from ACTIVE, or the S2R states. In order to stay in the mission state of STANDBY and not enter the hardware state LP_STANDBY, the LP_STANDBY_SEL bit must be cleared. The STANDBY state turns off all regulators. Therefore, it is required to select the state that the STANDBY state returns to. When the ENABLE pin goes low, the orderlyOff sequence is triggered. When the ENABLE pin goes high again, the destination state is dependent upon the STARTUP_DEST bits. The orderlyOff sequence is also triggered by the I2C_0 trigger. In this example, I2C_0 trigger is used to enter the STANDBY state. Write 0x48:0xC3:0x00:0xF7 // LP_STANDBY_SEL=0 Write 0x48:0x85:0x01:0xFE // set I2C_0 trigger, trigger orderlyOff sequence Once the PMIC is in Standby state, a wakeup request can be triggered with a rising edge on the Enable pin. Entering and Existing LP_STANDBY Entering the LP_STANDBY hardware state follows the same power-down sequence as entering STANDBY. Exiting LP_STANDBY is different and requires different initializations before entering LP_STANDBY. When entering LP_STANDBY, the PFSM automatically transitions to the hardware FSM state of SAFE_RECOVERY. From the SAFE_RECOVERY state, the recovery counter is incremented and compared to the recovery count threshold (see RECOV_CNT_REG_2, in ). If the recovery count threshold is reached, then the PMICs halt recovery attempts and require a power cycle. Refer to the data sheet for more details.Write 0x48:0xC3:0x08:0xF7 // LP_STANDBY_SEL=1 Write 0x48:0xC3:0x60;0x9F // Set the STARTUP_DEST=ACTIVE Write 0x48:0x85:0x01:0xFE // set I2C_0 trigger Application Examples This section provides examples of how to interact with the PMICs from the perspective of the MCU and over I2C. #GUID-D5C06820-6F5D-429A-B389-914AFCC7F5EA/GUID-D13CC848-0A7B-45ED-BFB8-0F5A5B93761C shows how the I2C commands are presented in the following sections. These examples, when used in conjunction with the data sheet, can be generalized and applied to other use cases. I²C Instruction Format I2C Address Register Address Data Mask 0x48 or 0x4C 0x00 - 0xFF 0x00 - 0xFF 0x00 - 0xFF This section provides examples of how to interact with the PMICs from the perspective of the MCU and over I2C. #GUID-D5C06820-6F5D-429A-B389-914AFCC7F5EA/GUID-D13CC848-0A7B-45ED-BFB8-0F5A5B93761C shows how the I2C commands are presented in the following sections. These examples, when used in conjunction with the data sheet, can be generalized and applied to other use cases. I²C Instruction Format I2C Address Register Address Data Mask 0x48 or 0x4C 0x00 - 0xFF 0x00 - 0xFF 0x00 - 0xFF This section provides examples of how to interact with the PMICs from the perspective of the MCU and over I2C. #GUID-D5C06820-6F5D-429A-B389-914AFCC7F5EA/GUID-D13CC848-0A7B-45ED-BFB8-0F5A5B93761C shows how the I2C commands are presented in the following sections. These examples, when used in conjunction with the data sheet, can be generalized and applied to other use cases.2#GUID-D5C06820-6F5D-429A-B389-914AFCC7F5EA/GUID-D13CC848-0A7B-45ED-BFB8-0F5A5B93761C2data sheet I²C Instruction Format I2C Address Register Address Data Mask 0x48 or 0x4C 0x00 - 0xFF 0x00 - 0xFF 0x00 - 0xFF I²C Instruction Format2 I2C Address Register Address Data Mask 0x48 or 0x4C 0x00 - 0xFF 0x00 - 0xFF 0x00 - 0xFF I2C Address Register Address Data Mask I2C Address Register Address Data Mask I2C AddressRegister AddressDataMask 0x48 or 0x4C 0x00 - 0xFF 0x00 - 0xFF 0x00 - 0xFF 0x48 or 0x4C 0x00 - 0xFF 0x00 - 0xFF 0x00 - 0xFF 0x48 or 0x4C0x00 - 0xFF0x00 - 0xFF0x00 - 0xFF Entering and Exiting S2R (Suspend to RAM) The default configuration of the NVM transitions the PMICs to the ACTIVE state when the ENABLE pin on the TPS65931211 goes high. The nINT pin goes low to indicate that an interrupt has occurred in the PMICs. After a normal power up sequence the BIST_PASS_INT field in the INT_MISC register is set. This interrupt bit indicates that BIST has been completed. Once the BIST_PASS_INT is cleared, the nINT pin is released (goes high) and PMIC can transition to a different state like S2R or Standby. The following section describe how to enter and exit the S2R state by hardware (using the GPIO3 pin) or by software (writing to the NSLEEP2B bit). State Table NSLEEP2(GPIO3) NSLEEP2B(register field) NSLEEP1B(register field) NSLEEP1_MASK(register field) NSLEEP2_MASK(register field) State / Trigger High Don't care Don't care 1 0 ACTIVE State /Trigger A Low 1 Don't care 1 0 ACTIVE State /Trigger A Low 0 Don't care 1 0 S2R State / Trigger D The NSLEEP1_MASK bit on register CONFIG_1 is set by default so the NSLEEP1 trigger does not affect FSM state transition. The mask settings can be changed by I2C when the PMIC is in Active state. The following code block shows how to execute triggers A and D using I2C commands to transition in and out of the S2R state. In this example the, PMIC is already in the S2R state after the GPIO3 was pulled low. The NSLEEP2B register field has effect only if GPO3 (NSLEEP2) is low. Write 0x48:0x86:0x01:0xFE // Set NSLEEP2B to transition out of the S2R state (Trigger A) Write 0x48:0x86:0x00:0xFE // Clear NSLEEP2B to trigger "any2_s2r" sequence (Trigger D) Instead of writing to the NSLEEP2B bit to return to the ACTIVE state, it is also possible to use the GPIO3 pin to return the PMIC to the ACTIVE state. Entering and Exiting S2R (Suspend to RAM) The default configuration of the NVM transitions the PMICs to the ACTIVE state when the ENABLE pin on the TPS65931211 goes high. The nINT pin goes low to indicate that an interrupt has occurred in the PMICs. After a normal power up sequence the BIST_PASS_INT field in the INT_MISC register is set. This interrupt bit indicates that BIST has been completed. Once the BIST_PASS_INT is cleared, the nINT pin is released (goes high) and PMIC can transition to a different state like S2R or Standby. The following section describe how to enter and exit the S2R state by hardware (using the GPIO3 pin) or by software (writing to the NSLEEP2B bit). State Table NSLEEP2(GPIO3) NSLEEP2B(register field) NSLEEP1B(register field) NSLEEP1_MASK(register field) NSLEEP2_MASK(register field) State / Trigger High Don't care Don't care 1 0 ACTIVE State /Trigger A Low 1 Don't care 1 0 ACTIVE State /Trigger A Low 0 Don't care 1 0 S2R State / Trigger D The NSLEEP1_MASK bit on register CONFIG_1 is set by default so the NSLEEP1 trigger does not affect FSM state transition. The mask settings can be changed by I2C when the PMIC is in Active state. The following code block shows how to execute triggers A and D using I2C commands to transition in and out of the S2R state. In this example the, PMIC is already in the S2R state after the GPIO3 was pulled low. The NSLEEP2B register field has effect only if GPO3 (NSLEEP2) is low. Write 0x48:0x86:0x01:0xFE // Set NSLEEP2B to transition out of the S2R state (Trigger A) Write 0x48:0x86:0x00:0xFE // Clear NSLEEP2B to trigger "any2_s2r" sequence (Trigger D) Instead of writing to the NSLEEP2B bit to return to the ACTIVE state, it is also possible to use the GPIO3 pin to return the PMIC to the ACTIVE state. The default configuration of the NVM transitions the PMICs to the ACTIVE state when the ENABLE pin on the TPS65931211 goes high. The nINT pin goes low to indicate that an interrupt has occurred in the PMICs. After a normal power up sequence the BIST_PASS_INT field in the INT_MISC register is set. This interrupt bit indicates that BIST has been completed. Once the BIST_PASS_INT is cleared, the nINT pin is released (goes high) and PMIC can transition to a different state like S2R or Standby. The following section describe how to enter and exit the S2R state by hardware (using the GPIO3 pin) or by software (writing to the NSLEEP2B bit). State Table NSLEEP2(GPIO3) NSLEEP2B(register field) NSLEEP1B(register field) NSLEEP1_MASK(register field) NSLEEP2_MASK(register field) State / Trigger High Don't care Don't care 1 0 ACTIVE State /Trigger A Low 1 Don't care 1 0 ACTIVE State /Trigger A Low 0 Don't care 1 0 S2R State / Trigger D The NSLEEP1_MASK bit on register CONFIG_1 is set by default so the NSLEEP1 trigger does not affect FSM state transition. The mask settings can be changed by I2C when the PMIC is in Active state. The following code block shows how to execute triggers A and D using I2C commands to transition in and out of the S2R state. In this example the, PMIC is already in the S2R state after the GPIO3 was pulled low. The NSLEEP2B register field has effect only if GPO3 (NSLEEP2) is low. Write 0x48:0x86:0x01:0xFE // Set NSLEEP2B to transition out of the S2R state (Trigger A) Write 0x48:0x86:0x00:0xFE // Clear NSLEEP2B to trigger "any2_s2r" sequence (Trigger D) Instead of writing to the NSLEEP2B bit to return to the ACTIVE state, it is also possible to use the GPIO3 pin to return the PMIC to the ACTIVE state. The default configuration of the NVM transitions the PMICs to the ACTIVE state when the ENABLE pin on the TPS65931211 goes high. The nINT pin goes low to indicate that an interrupt has occurred in the PMICs. After a normal power up sequence the BIST_PASS_INT field in the INT_MISC register is set. This interrupt bit indicates that BIST has been completed. Once the BIST_PASS_INT is cleared, the nINT pin is released (goes high) and PMIC can transition to a different state like S2R or Standby. The following section describe how to enter and exit the S2R state by hardware (using the GPIO3 pin) or by software (writing to the NSLEEP2B bit). State Table NSLEEP2(GPIO3) NSLEEP2B(register field) NSLEEP1B(register field) NSLEEP1_MASK(register field) NSLEEP2_MASK(register field) State / Trigger High Don't care Don't care 1 0 ACTIVE State /Trigger A Low 1 Don't care 1 0 ACTIVE State /Trigger A Low 0 Don't care 1 0 S2R State / Trigger D State Table NSLEEP2(GPIO3) NSLEEP2B(register field) NSLEEP1B(register field) NSLEEP1_MASK(register field) NSLEEP2_MASK(register field) State / Trigger High Don't care Don't care 1 0 ACTIVE State /Trigger A Low 1 Don't care 1 0 ACTIVE State /Trigger A Low 0 Don't care 1 0 S2R State / Trigger D NSLEEP2(GPIO3) NSLEEP2B(register field) NSLEEP1B(register field) NSLEEP1_MASK(register field) NSLEEP2_MASK(register field) State / Trigger NSLEEP2(GPIO3) NSLEEP2B(register field) NSLEEP1B(register field) NSLEEP1_MASK(register field) NSLEEP2_MASK(register field) State / Trigger NSLEEP2(GPIO3) (GPIO3)NSLEEP2B(register field) (register field)NSLEEP1B(register field) (register field)NSLEEP1_MASK(register field) (register field)NSLEEP2_MASK(register field) (register field)State / Trigger High Don't care Don't care 1 0 ACTIVE State /Trigger A Low 1 Don't care 1 0 ACTIVE State /Trigger A Low 0 Don't care 1 0 S2R State / Trigger D High Don't care Don't care 1 0 ACTIVE State /Trigger A HighDon't careDon't care10ACTIVE State /Trigger A Trigger A Low 1 Don't care 1 0 ACTIVE State /Trigger A Low1Don't care10ACTIVE State /Trigger A Trigger A Low 0 Don't care 1 0 S2R State / Trigger D Low0Don't care10S2R State / Trigger D Trigger DThe NSLEEP1_MASK bit on register CONFIG_1 is set by default so the NSLEEP1 trigger does not affect FSM state transition. The mask settings can be changed by I2C when the PMIC is in Active state. The following code block shows how to execute triggers A and D using I2C commands to transition in and out of the S2R state. In this example the, PMIC is already in the S2R state after the GPIO3 was pulled low. The NSLEEP2B register field has effect only if GPO3 (NSLEEP2) is low. Write 0x48:0x86:0x01:0xFE // Set NSLEEP2B to transition out of the S2R state (Trigger A) Write 0x48:0x86:0x00:0xFE // Clear NSLEEP2B to trigger "any2_s2r" sequence (Trigger D) Instead of writing to the NSLEEP2B bit to return to the ACTIVE state, it is also possible to use the GPIO3 pin to return the PMIC to the ACTIVE state. Entering and Exiting Standby STANDBY can be entered from ACTIVE, or the S2R states. In order to stay in the mission state of STANDBY and not enter the hardware state LP_STANDBY, the LP_STANDBY_SEL bit must be cleared. The STANDBY state turns off all regulators. Therefore, it is required to select the state that the STANDBY state returns to. When the ENABLE pin goes low, the orderlyOff sequence is triggered. When the ENABLE pin goes high again, the destination state is dependent upon the STARTUP_DEST bits. The orderlyOff sequence is also triggered by the I2C_0 trigger. In this example, I2C_0 trigger is used to enter the STANDBY state. Write 0x48:0xC3:0x00:0xF7 // LP_STANDBY_SEL=0 Write 0x48:0x85:0x01:0xFE // set I2C_0 trigger, trigger orderlyOff sequence Once the PMIC is in Standby state, a wakeup request can be triggered with a rising edge on the Enable pin. Entering and Exiting Standby STANDBY can be entered from ACTIVE, or the S2R states. In order to stay in the mission state of STANDBY and not enter the hardware state LP_STANDBY, the LP_STANDBY_SEL bit must be cleared. The STANDBY state turns off all regulators. Therefore, it is required to select the state that the STANDBY state returns to. When the ENABLE pin goes low, the orderlyOff sequence is triggered. When the ENABLE pin goes high again, the destination state is dependent upon the STARTUP_DEST bits. The orderlyOff sequence is also triggered by the I2C_0 trigger. In this example, I2C_0 trigger is used to enter the STANDBY state. Write 0x48:0xC3:0x00:0xF7 // LP_STANDBY_SEL=0 Write 0x48:0x85:0x01:0xFE // set I2C_0 trigger, trigger orderlyOff sequence Once the PMIC is in Standby state, a wakeup request can be triggered with a rising edge on the Enable pin. STANDBY can be entered from ACTIVE, or the S2R states. In order to stay in the mission state of STANDBY and not enter the hardware state LP_STANDBY, the LP_STANDBY_SEL bit must be cleared. The STANDBY state turns off all regulators. Therefore, it is required to select the state that the STANDBY state returns to. When the ENABLE pin goes low, the orderlyOff sequence is triggered. When the ENABLE pin goes high again, the destination state is dependent upon the STARTUP_DEST bits. The orderlyOff sequence is also triggered by the I2C_0 trigger. In this example, I2C_0 trigger is used to enter the STANDBY state. Write 0x48:0xC3:0x00:0xF7 // LP_STANDBY_SEL=0 Write 0x48:0x85:0x01:0xFE // set I2C_0 trigger, trigger orderlyOff sequence Once the PMIC is in Standby state, a wakeup request can be triggered with a rising edge on the Enable pin. STANDBY can be entered from ACTIVE, or the S2R states. In order to stay in the mission state of STANDBY and not enter the hardware state LP_STANDBY, the LP_STANDBY_SEL bit must be cleared.The STANDBY state turns off all regulators. Therefore, it is required to select the state that the STANDBY state returns to. When the ENABLE pin goes low, the orderlyOff sequence is triggered. When the ENABLE pin goes high again, the destination state is dependent upon the STARTUP_DEST bits. The orderlyOff sequence is also triggered by the I2C_0 trigger. In this example, I2C_0 trigger is used to enter the STANDBY state. Write 0x48:0xC3:0x00:0xF7 // LP_STANDBY_SEL=0 Write 0x48:0x85:0x01:0xFE // set I2C_0 trigger, trigger orderlyOff sequence Once the PMIC is in Standby state, a wakeup request can be triggered with a rising edge on the Enable pin. Write 0x48:0xC3:0x00:0xF7 // LP_STANDBY_SEL=0 Write 0x48:0x85:0x01:0xFE // set I2C_0 trigger, trigger orderlyOff sequence Once the PMIC is in Standby state, a wakeup request can be triggered with a rising edge on the Enable pin.Once the PMIC is in Standby state, a wakeup request can be triggered with a rising edge on the Enable pin. Entering and Existing LP_STANDBY Entering the LP_STANDBY hardware state follows the same power-down sequence as entering STANDBY. Exiting LP_STANDBY is different and requires different initializations before entering LP_STANDBY. When entering LP_STANDBY, the PFSM automatically transitions to the hardware FSM state of SAFE_RECOVERY. From the SAFE_RECOVERY state, the recovery counter is incremented and compared to the recovery count threshold (see RECOV_CNT_REG_2, in ). If the recovery count threshold is reached, then the PMICs halt recovery attempts and require a power cycle. Refer to the data sheet for more details.Write 0x48:0xC3:0x08:0xF7 // LP_STANDBY_SEL=1 Write 0x48:0xC3:0x60;0x9F // Set the STARTUP_DEST=ACTIVE Write 0x48:0x85:0x01:0xFE // set I2C_0 trigger Entering and Existing LP_STANDBY Entering the LP_STANDBY hardware state follows the same power-down sequence as entering STANDBY. Exiting LP_STANDBY is different and requires different initializations before entering LP_STANDBY. When entering LP_STANDBY, the PFSM automatically transitions to the hardware FSM state of SAFE_RECOVERY. From the SAFE_RECOVERY state, the recovery counter is incremented and compared to the recovery count threshold (see RECOV_CNT_REG_2, in ). If the recovery count threshold is reached, then the PMICs halt recovery attempts and require a power cycle. Refer to the data sheet for more details.Write 0x48:0xC3:0x08:0xF7 // LP_STANDBY_SEL=1 Write 0x48:0xC3:0x60;0x9F // Set the STARTUP_DEST=ACTIVE Write 0x48:0x85:0x01:0xFE // set I2C_0 trigger Entering the LP_STANDBY hardware state follows the same power-down sequence as entering STANDBY. Exiting LP_STANDBY is different and requires different initializations before entering LP_STANDBY. When entering LP_STANDBY, the PFSM automatically transitions to the hardware FSM state of SAFE_RECOVERY. From the SAFE_RECOVERY state, the recovery counter is incremented and compared to the recovery count threshold (see RECOV_CNT_REG_2, in ). If the recovery count threshold is reached, then the PMICs halt recovery attempts and require a power cycle. Refer to the data sheet for more details.Write 0x48:0xC3:0x08:0xF7 // LP_STANDBY_SEL=1 Write 0x48:0xC3:0x60;0x9F // Set the STARTUP_DEST=ACTIVE Write 0x48:0x85:0x01:0xFE // set I2C_0 trigger Entering the LP_STANDBY hardware state follows the same power-down sequence as entering STANDBY. Exiting LP_STANDBY is different and requires different initializations before entering LP_STANDBY. When entering LP_STANDBY, the PFSM automatically transitions to the hardware FSM state of SAFE_RECOVERY. From the SAFE_RECOVERY state, the recovery counter is incremented and compared to the recovery count threshold (see RECOV_CNT_REG_2, in ). If the recovery count threshold is reached, then the PMICs halt recovery attempts and require a power cycle. Refer to the data sheet for more details.Write 0x48:0xC3:0x08:0xF7 // LP_STANDBY_SEL=1 Write 0x48:0xC3:0x60;0x9F // Set the STARTUP_DEST=ACTIVE Write 0x48:0x85:0x01:0xFE // set I2C_0 trigger data sheetWrite 0x48:0xC3:0x08:0xF7 // LP_STANDBY_SEL=1 Write 0x48:0xC3:0x60;0x9F // Set the STARTUP_DEST=ACTIVE Write 0x48:0x85:0x01:0xFE // set I2C_0 trigger References For additional information regarding the PMIC or processor devices, use the following: Texas Instruments, AM62A starter kit for low-power Sitara processors Texas Instruments, TPS6593 Data sheet Texas Instruments, TPS6593-Q1 Safety Manual (request through mySecure) Texas Instruments, AM62Ax Data sheet Texas Instruments, AM62Ax Sitara Processors Technical Reference Manual References For additional information regarding the PMIC or processor devices, use the following: Texas Instruments, AM62A starter kit for low-power Sitara processors Texas Instruments, TPS6593 Data sheet Texas Instruments, TPS6593-Q1 Safety Manual (request through mySecure) Texas Instruments, AM62Ax Data sheet Texas Instruments, AM62Ax Sitara Processors Technical Reference Manual For additional information regarding the PMIC or processor devices, use the following: Texas Instruments, AM62A starter kit for low-power Sitara processors Texas Instruments, TPS6593 Data sheet Texas Instruments, TPS6593-Q1 Safety Manual (request through mySecure) Texas Instruments, AM62Ax Data sheet Texas Instruments, AM62Ax Sitara Processors Technical Reference Manual Texas Instruments, AM62A starter kit for low-power Sitara processors Texas Instruments, TPS6593 Data sheet Texas Instruments, TPS6593-Q1 Safety Manual (request through mySecure) Texas Instruments, AM62Ax Data sheet Texas Instruments, AM62Ax Sitara Processors Technical Reference Manual Texas Instruments, AM62A starter kit for low-power Sitara processors AM62A starter kit for low-power Sitara processorsTexas Instruments, TPS6593 Data sheet TPS6593 Data sheetTexas Instruments, TPS6593-Q1 Safety Manual (request through mySecure)Texas Instruments, AM62Ax Data sheet AM62Ax Data sheetTexas Instruments, AM62Ax Sitara Processors Technical Reference Manual AM62Ax Sitara Processors Technical Reference Manual IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.TI’s Terms of Saleti.com TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Copyright © 2023, Texas Instruments Incorporated.

Figure 6-1 Pre-Configurable Finite State Machine (PFSM) Mission States and Transitions

When the PMICs transition from the FSM to the PFSM, it waits for a valid ON Request before entering the ACTIVE state. The definition for each power state is described below: