SLVUCM3 july   2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , TPS6593-Q1

 

  1.   1
  2.   User's Guide for Powering AM62A with TPS65931211-Q1 PMIC
  3.   Trademarks
  4. 1Introduction
  5. 2Device Versions
  6. 3Processor Connections
    1. 3.1 Power Mapping
      1. 3.1.1 Supporting 0.85V on VDD_CORE
      2. 3.1.2 Using 5V Input Supply
    2. 3.2 Control Mapping
  7. 4Supporting Functional Safety ASIL-B Requirements
  8. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Watchdog Settings
  9. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 Sequence: immediateOff2Safe_pd
      2. 6.3.2 Sequence: orderlyOff2safe
      3. 6.3.3 Sequence: warmReset
      4. 6.3.4 Sequence: any2active
      5. 6.3.5 Sequence: any2_s2r
  10. 7Application Examples
    1. 7.1 Entering and Exiting S2R (Suspend to RAM)
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
  11. 8References

3.1 Power Mapping

Figure 3-1 shows the power mapping between the TPS65931211-Q1 PMIC power resources and processor voltage domains. Some of the external peripherals like uSD card, Ethernet PHY and HDMI are optional and might not be needed for the end product. These optional systems peripherals were included in the AM62A SK EVM for development and testing purposes.

This PDN uses the TPS6593-Q1 PMIC and discrete power components to meet the power/sequence requirements of the processor and system peripherals. Some of the discrete components are optional depending upon end product features. In this configuration, PMIC uses a 3.3 V input voltage. The TPS22965 Load Switch connects the 3.3V pre-regulator (VSYS_3V3) to the processor 3.3V IO domains. The unused feedback pin, FB_B3, of the TPS65931211-Q1 has been configured per NVM settings, Table 5-3, to provide voltage monitoring for the 3.3V IO domain. This monitoring function enables all of the processor CORE, digital and analog supplies to have voltage monitoring coverage as needed for functional safety ASIL-B systems.

LDO1 of the TPS65931211-Q1 PMIC is configured as bypass to supply the SD card dual-voltage I/O (3.3 V and 1.8 V). A processor GPIO control signal with a logic high default value and an external pull-up is used to set SD IO to 3.3 V initially. After the power-up sequence, the processor can set GPIO signal low to select 1.8 V level as needed for high-speed card operation per SD specification. This bypass configuration allows control of the LDO1 voltage from 3.3V to 1.8V without the need to establish I2C communication during boot from SD card operations. The bypass configuration on LDO1 requires connecting its input supply pin (PVIN_LDO12) to 3.3V.

The AM62A processor supports multiple low power modes. For the Partial I/O low power mode, the entire SoC is OFF except I/O pins in CANUART I/O bank to maintain wakeup capability. This mode is supported by turning OFF the PMIC and keeping the 3.3V pre-regulator ON to supply VDDSHV_CANUART (3.3V) and an external discrete to supply VDD_CANUART (0.75 V or 0.85 V).

Note: The PMIC voltage monitor on FB_B3 must be connected to 3.3 V. If 3.3 V is not connected to FB_B3 when the monitor is enabled then the device goes to the hardware SAFE RECOVERY state, and the processor voltages are disabled.
GUID-20221110-SS0I-NWLB-L2ZF-WFF9JZHW3RBQ-low.svg
Note: The external discrete that supplies VDD_CANUART is only needed for Partial IO. When not using Partial IO, VDD_CANUART needs to be connected to the multi-phase Buck1/2/3 and VDDSHV_CANUART can be connected to the same 3.3 V rail that supplies the DVDD3V3(VDDSHVx).
Figure 3-1 Example Power Connections

Table 3-1 identifies which power resources are required to support different system features.

Table 3-1 PDN Power Mapping and System Features
Power Mapping System Features (1)
Device Power Resource Voltage Processor Domains Active SoC Partial IO

(Low Power Mode)

 IO + DDR

(Low Power Mode)

 SD Card interface
3.3V pre-regulator

(LM5141-Q1)

 BUCK 3.3V VDDSHV_CANUART

PMIC Supply

 R R R
TLV705075 LDO 0.75V VDD_CANUART R R R
TPS65931211-Q1 BUCK123 0.75V or 0.85V

(2)

 VDD_CORE R
VDDA_CORE_CSIRX0 R
VDDA_CORE_USB R
VDDA_DDR_PLL0 R
FB_B3 3.3V monitors 3.3V IO domain R R
BUCK4 1.1V or 1.2V VDDS_DDR R R
BUCK5 1.8V DVDD1V8(VDDSHVy) R R
VMON_1P8_SOC (3) O
LDO1 3.3V / 1.8V VDDSHV5 O R
LDO2 1.8V VPP (eFUSE) O
LDO3 0.85V

(2)

 VDDR_CORE R
LDO4 1.8V VDDA_1P8_USB R
VDDA_TEMP R
VDDS_OSC0 R
VDDA_MCU R
VDDA_PLL R
VDDA_1P8_CSIRX0 R
TPS22965-Q1 Load Switch 3.3V DVDD3V3(VDDSHVx) R
VDDSHV_MCU R
VMON_3P3_SOC (3) O
VDDA_3P3_USB R
TPS62824 BUCK 2.5V VDD_2V5_ETHERNET PHY O
TLV75510P LDO 1.0V VDD1P0_ETHERNET PHY O
TLV75512P LDO 1.2V CVCC12_HDMI TRANSMITTER O
(1) 'R' is required and 'O' is optional.
(2) If the multiphase Buck1/2/3 is configured to output 0.85V, both CORE rails on the AM62A (VDD_CORE and VDDR_CORE) are supplied by Buck1/2/3. In this case, LDO3 becomes a free power resource.
(3) VMON_3P3_SOC and VMON_1P8_SOC are not supply pins but voltage monitor inputs for the 1.8 V and 3.3 V SoC power supply. If VMON_1P8_SOC and VMON_3P3_SOC are not used to monitor the SOC power rails, they must still be connected to their respective 1.8V and 3.3V power rails.