SLVUCM3 july   2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , TPS6593-Q1

 

  1.   1
  2.   User's Guide for Powering AM62A with TPS65931211-Q1 PMIC
  3.   Trademarks
  4. 1Introduction
  5. 2Device Versions
  6. 3Processor Connections
    1. 3.1 Power Mapping
      1. 3.1.1 Supporting 0.85V on VDD_CORE
      2. 3.1.2 Using 5V Input Supply
    2. 3.2 Control Mapping
  7. 4Supporting Functional Safety ASIL-B Requirements
  8. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Watchdog Settings
  9. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 Sequence: immediateOff2Safe_pd
      2. 6.3.2 Sequence: orderlyOff2safe
      3. 6.3.3 Sequence: warmReset
      4. 6.3.4 Sequence: any2active
      5. 6.3.5 Sequence: any2_s2r
  10. 7Application Examples
    1. 7.1 Entering and Exiting S2R (Suspend to RAM)
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
  11. 8References

2 Device Versions

There are different orderable part numbers (OPNs) of the TPS6593-Q1 device available with unique NVM settings to support different end product use cases and processor types. The unique NVM settings for each PMIC device are optimized per PDN design to support different processors, processing loads, SDRAM types, system functional safety levels, and end product features (such as low power modes, processor voltages, and memory subsystems). The NVM settings can be identified by both NVM_ID and NVM_REV registers. Each TPS6593 PMIC device is distinguished by the part number, NVM_ID, and NVM_REV.

Table 2-1 TPS6593-Q1 Orderable Part Number for AM62A
PDN USE CASE Orderable Part Number TI_NVM_ID

(TI_NVM_REV)
  • Supports Functional Safety up to ASIL-B level.
  • Supports AM62A low power modes (including Partial IO and Suspend to RAM).
  • Up to 10.5 A(1) in multiphase (3-phase) configuration to supply the processor CORE rail with selectable 0.75V or 0.85V.
  • Up to 4 A(1) to supply the VDDS_DDR with selectable 1.1V for LPDDR4.
  • Supports I/O level of 3.3 V and 1.8 V.
  • Supports optional end product features:
    • Compliant high-speed SD Card memory
    • eMMC
    • eFuse ROM programming supply
    • Compliant USB 2.0 Interface
    • Ethernet PHY
    • HDMI
 TPS65931211 RWERQ1 0x11 (0x05)
(1) TI recommends having 15% margin between the maximum expected load current and the maximum current allowed per each PMIC output rail.