SLVUCM3 july   2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , TPS6593-Q1

 

  1.   1
  2.   User's Guide for Powering AM62A with TPS65931211-Q1 PMIC
  3.   Trademarks
  4. 1Introduction
  5. 2Device Versions
  6. 3Processor Connections
    1. 3.1 Power Mapping
      1. 3.1.1 Supporting 0.85V on VDD_CORE
      2. 3.1.2 Using 5V Input Supply
    2. 3.2 Control Mapping
  7. 4Supporting Functional Safety ASIL-B Requirements
  8. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Watchdog Settings
  9. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 Sequence: immediateOff2Safe_pd
      2. 6.3.2 Sequence: orderlyOff2safe
      3. 6.3.3 Sequence: warmReset
      4. 6.3.4 Sequence: any2active
      5. 6.3.5 Sequence: any2_s2r
  10. 7Application Examples
    1. 7.1 Entering and Exiting S2R (Suspend to RAM)
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
  11. 8References

7.1 Entering and Exiting S2R (Suspend to RAM)

The default configuration of the NVM transitions the PMICs to the ACTIVE state when the ENABLE pin on the TPS65931211 goes high. The nINT pin goes low to indicate that an interrupt has occurred in the PMICs. After a normal power up sequence the BIST_PASS_INT field in the INT_MISC register is set. This interrupt bit indicates that BIST has been completed. Once the BIST_PASS_INT is cleared, the nINT pin is released (goes high) and PMIC can transition to a different state like S2R or Standby. The following section describe how to enter and exit the S2R state by hardware (using the GPIO3 pin) or by software (writing to the NSLEEP2B bit).

Table 7-2 State Table
NSLEEP2

(GPIO3)

 NSLEEP2B

(register field)

 NSLEEP1B

(register field)

 NSLEEP1_MASK

(register field)

 NSLEEP2_MASK

(register field)

 State / Trigger
High Don't care Don't care 1 0 ACTIVE State /

Trigger A
Low 1 Don't care 1 0 ACTIVE State /

Trigger A
Low 0 Don't care 1 0 S2R State /

Trigger D
Note: The NSLEEP1_MASK bit on register CONFIG_1 is set by default so the NSLEEP1 trigger does not affect FSM state transition. The mask settings can be changed by I2C when the PMIC is in Active state.

The following code block shows how to execute triggers A and D using I2C commands to transition in and out of the S2R state. In this example the, PMIC is already in the S2R state after the GPIO3 was pulled low. The NSLEEP2B register field has effect only if GPO3 (NSLEEP2) is low. 

Write 0x48:0x86:0x01:0xFE  // Set NSLEEP2B to transition out of the S2R state (Trigger A)
Write 0x48:0x86:0x00:0xFE // Clear NSLEEP2B to trigger "any2_s2r" sequence (Trigger D)

Instead of writing to the NSLEEP2B bit to return to the ACTIVE state, it is also possible to use the GPIO3 pin to return the PMIC to the ACTIVE state.