SLVUCN1 January   2023 TLVM13610

 

  1.   Abstract
  2.   Trademarks
  3. 1High-Density EVM Description
    1. 1.1 Typical Applications
  4. 2Test Setup and Procedure
    1. 2.1 EVM Connections
    2. 2.2 EVM Setup
    3. 2.3 Test Equipment
    4. 2.4 Recommended Test Setup
      1. 2.4.1 Input Connections
      2. 2.4.2 Output Connections
    5. 2.5 Test Procedure
      1. 2.5.1 Line, Load Regulation and Efficiency
  5. 3Test Data and Performance Curves
    1. 3.1 Efficiency and Load Regulation Performance
    2. 3.2 Waveforms
    3. 3.3 Bode Plot
    4. 3.4 EMI Performance
  6. 4EVM Documentation
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout
    4. 4.4 Multi-Layer Stackup
  7. 5Device and Documentation Support
    1. 5.1 Device Support
      1. 5.1.1 Development Support
        1. 5.1.1.1 Custom Design With WEBENCH® Tools
    2. 5.2 Documentation Support
      1. 5.2.1 Related Documentation

1 High-Density EVM Description

The TLVM13610EVM features the TLVM13610 synchronous buck power module configured for operation with typical 3-V to 36-V input bus applications. This wide-VIN range DC/DC solution offers outsized voltage rating and operating margin to withstand supply-rail voltage transients.

The output voltage can be set to either 3.3 V or 5 V and switching frequency can each be set to one of five popular values (400 kHz, 700 kHz, 1 MHz, 1.4 MHz, and 2.2 MHz) by using configuration jumpers. Additionally, a resistor placeholder footprint is on the backside of the EVM to allow adjustment of the switching frequency outside of the five jumper settings.

The EVM provides the full 8-A output current rating of the device. The selected input and output capacitors accommodate the entire range of input voltage and the selectable output voltages on the EVM and are available from multiple component vendors. Input and output voltage sense terminals and a test point header facilitate measurement of the following:

  • Efficiency and power dissipation
  • Line and load regulation
  • Load transient response
  • Enable ON, OFF
  • Bode plot (crossover frequency and phase margin)
PCB layout maximizes thermal performance and minimizes output ripple and noise.