SLVUCP0A December   2023  – March 2024 TPS22996

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Setup
    2. 2.2 Operation
  8. 3Implementation Results
    1. 3.1 Electrical Performance
    2. 3.2 Test Configurations
      1. 3.2.1 Rise Time Test Setup
  9. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials (BOM)
  10. 5Additional Information
    1. 5.1 Trademarks
  11. 6Revision History

2.1 Setup

This section describes the jumpers and connectors on the EVM as well as how to properly connect, set up and use the EVM. Table 3-1 describes the input and output connectors and jumpers. Table 3-2 describes the different test points and functionality. Table 3-3 describes the jumper functionality and configurations.

Table 2-1 TPS22996EVM Input and Output Connector Functionality
InputConnector and Test PointLabelDescription
VINx

VBIAS

J1, J2, J3VSUP1, VSUP2, VSUP3Input banana connectors for VINx and VBIAS
J6, J7J6, J7Input selectors for VINx and VBIAS
TP3, TP4, TP5VIN1, VIN2, VBIASInput test points for VINx and VBIAS
VONxJ4J4Input header for ONx signals
J8, J9J8, J9ON signal source selections
TP1, TP2VON1, VON2Input test points for VONx
SW1. SW2SW1, SW2Current-limit resistor selector
VOUTxJ10, J12VOUT1, VOUT2Output banana connectors for VOUTx
TP6, TP7VOUT1, VOUT2Output test points for VOUTx
GNDJ5, J11, J13GNDBanana connectors for GND
TP8, TP9, TP10GNDTest points for GND
Table 2-2 TPS22996EVM Test Point Description
PinTest PointLabelDescription
ENTP13ONEnable signal test point
VBIASTP12VBIASBias voltage test point
PGTP14PGPower good signal test point
Table 2-3 TPS22996EVM Jumper Configuration
InputJumperLabelDescription
VINJP2EN_SELON-pin enable signal
  • Position 1 and 2 pulls ON-pin LO
  • Position 2 and 3 pulls ON-pin to VIN
VOUT and VBIASJP1PG_PU_SELPG pullup setting
  • Position 1 and 2 pulls PG-pin to VBIAS
  • Position 2 and 3 pulls PG-pin to VOUT