SLVUCQ2A
july 2023 – july 2023
TPSF12C1
,
TPSF12C1-Q1
1
Description
Get Started
Features
Applications
6
1
Evaluation Module Overview
1.1
Introduction
1.2
Kit Contents
1.3
Specifications
1.4
Device Information
General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
2
Hardware
2.1
EVM Description
2.2
Setup
2.3
Header Information
2.4
EVM Performance Validation
2.5
AEF Design Flow
2.5.1
AEF Circuit Optimization and Debug
3
Implementation Results
3.1
EMI Performance
3.2
Thermal Performance
3.3
Surge Immunity
3.4
SENSE and INJ Voltages
3.5
Insertion Loss
3.6
Passive vs. Active Solution Comparison
4
Hardware Design Files
4.1
Schematic
4.2
Bill of Materials
4.3
PCB Layout
4.3.1
Assembly Drawings
4.3.2
Multi-Layer Stackup
5
Compliance Information
5.1
Compliance and Certifications
6
Additional Information
Trademarks
7
Related Documentation
7.1
Supplemental Content
8
Revision History
Features
Improved CM
EMI performance
for applications with single-phase AC input
Voltage-sense, current-inject AEF topology presents low shunt impedance by amplifying the effective value of Y-capacitance
Up to 30 dB reduction in the CM EMI signature from 100 kHz to 3 MHz
A higher effective Y-capacitance enables a reduction in CM choke size, weight and cost
Simple configuration for single-phase AC systems
Integrated sensing filter and summing network
Low Y-capacitor line-frequency leakage current to chassis ground maintains safety
Simplified compensation network
Inherent protection features for reliable design
Withstands 6-kV+ surge with minimal external component count
Helps meet IEC 61000-4-5 surge immunity system-level specification
Integrated SENSE input surge protection
Wide VDD supply voltage range of 8 V to 16 V
Undervoltage lockout (UVLO) set to turn on and off at 7.7 V and 6.7 V, respectively
The EVM includes a high-PSRR LDO for step-down regulation to 12 V (if needed)
175°C thermal shutdown protection
Integrated VDD-to-EN pullup allows use of an open-drain/collector device for disable function
Fully assembled, tested and proven two-layer
PCB design
with 5" × 3" (127 mm × 76 mm) total area