SLVUCQ2A july   2023  – july 2023 TPSF12C1 , TPSF12C1-Q1

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
    5.     General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  8. 2Hardware
    1. 2.1 EVM Description
    2. 2.2 Setup
    3. 2.3 Header Information
    4. 2.4 EVM Performance Validation
    5. 2.5 AEF Design Flow
      1. 2.5.1 AEF Circuit Optimization and Debug
  9. 3Implementation Results
    1. 3.1 EMI Performance
    2. 3.2 Thermal Performance
    3. 3.3 Surge Immunity
    4. 3.4 SENSE and INJ Voltages
    5. 3.5 Insertion Loss
    6. 3.6 Passive vs. Active Solution Comparison
  10. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout
      1. 4.3.1 Assembly Drawings
      2. 4.3.2 Multi-Layer Stackup
  11. 5Compliance Information
    1. 5.1 Compliance and Certifications
  12. 6Additional Information
    1.     Trademarks
  13. 7Related Documentation
    1. 7.1 Supplemental Content
  14. 8Revision History

PCB Layout

Figure 5-2 through Figure 5-8 show the PCB layout images, including 3D views, copper layers, assembly drawings, and layer stackup diagram. The PCB is 62-mils standard thickness with 2-oz copper thickness on top and bottom layers. Review the Altium source files for more detail.

GUID-20230627-SS0I-6F0M-2STX-4H2PDV0CTXMJ-low.svg Figure 4-2 3D Top View
GUID-20230627-SS0I-BBQ4-CWJ0-2XGRV8R6ZRKK-low.svg Figure 4-3 3D Bottom View
GUID-20230627-SS0I-TP60-3KNB-TJRJFBLX0GSZ-low.svg Figure 4-4 Top Layer Copper
GUID-20230627-SS0I-HG5D-LX0N-KVCLLZPMRDTV-low.svg Figure 4-5 Bottom Layer Copper (Viewed From Top)