SLVUCQ2A july   2023  – july 2023 TPSF12C1 , TPSF12C1-Q1

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
    5.     General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  8. 2Hardware
    1. 2.1 EVM Description
    2. 2.2 Setup
    3. 2.3 Header Information
    4. 2.4 EVM Performance Validation
    5. 2.5 AEF Design Flow
      1. 2.5.1 AEF Circuit Optimization and Debug
  9. 3Implementation Results
    1. 3.1 EMI Performance
    2. 3.2 Thermal Performance
    3. 3.3 Surge Immunity
    4. 3.4 SENSE and INJ Voltages
    5. 3.5 Insertion Loss
    6. 3.6 Passive vs. Active Solution Comparison
  10. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout
      1. 4.3.1 Assembly Drawings
      2. 4.3.2 Multi-Layer Stackup
  11. 5Compliance Information
    1. 5.1 Compliance and Certifications
  12. 6Additional Information
    1.     Trademarks
  13. 7Related Documentation
    1. 7.1 Supplemental Content
  14. 8Revision History

3.3 Surge Immunity

Figure 4-8, Figure 4-4 and Figure 4-5 show surge immunity results. The CM chokes are shorted during this test, but the MOVs are installed as required.

GUID-20221029-SS0I-FM7S-0XDK-K2MCSQK99NP3-low.svg Figure 3-3 IEC 61000-4-5 Positive Surge, 6-kV Single Strike – 1 µs/div (a), 200 µs/div (b)
GUID-20221029-SS0I-DK1X-RRV4-0GZDWGTR4PRR-low.svg Figure 3-4 IEC 61000-4-5 Negative Surge, 6-kV Single Strike – 1 µs/div (a), 200 µs/div (b)
GUID-20221029-SS0I-ZQJD-CMNF-GMHGMWXPGP0Z-low.svg Figure 3-5 IEC 61000-4-5 Surge, 6-kV Repetitive Strike at 10-Second Intervals – Positive (a), Negative (b)