SLVUCQ2A july   2023  – july 2023 TPSF12C1 , TPSF12C1-Q1

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
    5.     General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  8. 2Hardware
    1. 2.1 EVM Description
    2. 2.2 Setup
    3. 2.3 Header Information
    4. 2.4 EVM Performance Validation
    5. 2.5 AEF Design Flow
      1. 2.5.1 AEF Circuit Optimization and Debug
  9. 3Implementation Results
    1. 3.1 EMI Performance
    2. 3.2 Thermal Performance
    3. 3.3 Surge Immunity
    4. 3.4 SENSE and INJ Voltages
    5. 3.5 Insertion Loss
    6. 3.6 Passive vs. Active Solution Comparison
  10. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout
      1. 4.3.1 Assembly Drawings
      2. 4.3.2 Multi-Layer Stackup
  11. 5Compliance Information
    1. 5.1 Compliance and Certifications
  12. 6Additional Information
    1.     Trademarks
  13. 7Related Documentation
    1. 7.1 Supplemental Content
  14. 8Revision History

2.2 Setup

Figure 3-2 shows a typical EMI measurement setup. A line impedance stabilization network (LISN) in series with each supply line enables measurement of the total EMI that includes DM and CM propagation components. A splitter/combiner can be used to extract the DM and CM noise signatures from the total noise measurement.

GUID-20230701-SS0I-GJFD-Z91Q-W7QQD9KX7TF9-low.svg Figure 2-2 EMI Measurement Setup for a Single-Phase System

The AC/DC regulator has internal high-dv/dt switching nodes that can capacitively couple CM noise to the chassis. As such, verifying the Y-capactiors in the EMI filter are closely referenced to the chassis is imperative, as illustrated in Figure 3-2. The Y-capacitors can then return the CM noise current back to the noise source in a tight conduction loop. Otherwise, the noise current can flow in the reference ground plane back to the LISNs, rendering the EMI filter less effective.

Figure 3-3 shows the recommended setup to evaluate the performance of the TPSF12C1 with a power stage connected.

GUID-20230629-SS0I-ZBR5-8N1N-ZPSC4KVPLKBW-low.svg Figure 2-3 EVM Setup Schematic for High-Voltage Testing with AC/DC Power Stage Connected

A two-phase interleaved boost PFC topology in Figure 3-3 represents a typical single-phase AC/DC regulator and is drawn for illustrative purposes. The setup is essentially agnostic to regulator topology.

Meanwhile, Figure 3-4 shows a schematic that is designed for low-voltage testing of the active filter design, including insertion loss measurement and EMI performance characterization. This facilitates an easy and convenient verification of the active filter circuit prior to connection to a high-voltage switching regulator. A good signal source and coupling capacitor provide CM excitation that mimics the CM noise source voltage and noise source impedance related to the switch-node behavior of an actual power stage.

GUID-20230630-SS0I-BCGW-MCLC-FPFZX3SSNNGK-low.svg Figure 2-4 EVM Setup Schematic for Low-Voltage Testing