Figure 4-2 to Figure 4-9 show the design of the TPS7H2140EVM printed-circuit board (PCB). The EVM has main power input and output connectors on the right side of the board, with auxiliary IO power inputs on the top. Jumpers for device configuration are located on the left side of the board, around the IC, and directly behind the output terminals. Vias under the TPS7H2140 allow a thermal path from the top layer all the way to the bottom layer. The EVM board utilizes a GND network to allow for testing of applications that can require one. However, if a GND network is not required for the application of the TPS7H2140-SEP, the thermal pad can also be connected directly to a GND plane to improve thermal performance. Additional information can be found in the Layout Examples section of the TPS7H2140-SEP data sheet. Pads are provided on the bottom of the EVM that can be populated with 0 Ω resistors to connect the output channels together in parallel, as well as pads on the top layer to synchronize the enable signals of the output channels.

Figure 4-2 Top Overlay

Figure 4-3 Top Solder Mask

Figure 4-4 Layer 1 (Top)

Figure 4-5 Layer 2

Figure 4-6 Layer 2

Figure 4-7 Layer 3 (Bottom)

Figure 4-8 Bottom Solder Mask

Figure 4-9 Bottom Overlay