SLVUCU6A November   2023  – October 2024

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Getting Started
    2. 2.2 EVM Details
      1. 2.2.1 Terminal Blocks
      2. 2.2.2 Test Point Descriptions
      3. 2.2.3 Configuration Headers
      4. 2.2.4 Connectors
      5. 2.2.5 Dip Switches
      6. 2.2.6 EVM Control and GPIO
    3. 2.3 Customization
      1. 2.3.1 Changing the Communication Interface
      2. 2.3.2 Changing the Phase Configuration
  9. 3Software
    1. 3.1 GUI Tool
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials
  11. 5Additional Information
    1.     Trademarks
  12. 6Related Documentation
  13. 7Revision History

2.2.2 Test Point Descriptions

Numerous test points are provided to access voltages and signals. Test points marked with _S are designed for sensing voltages only and are not designed to carry large DC currents.

Table 2-2 Test Point Descriptions
Test PointDevice PinDescription
TP1VOUT_LDO_SVoltage sense point for the internal LDO.
TP2, TP6, TP8, TP10, TP13, TP14, TP16, GND_SGround sense points routed from various locations.
TP3VIO_SVIO voltage sense routed from the VIO pin of the TP65224-Q1
TP5, J35 (Right pin)VCCA_SVCCA voltage sense point.
TP9, TP11, TP12, TP15GNDSolid ground points. Are able to carry larger DC currents.
J3, J7, J8, J15FB_B1, FB_B2, FB_B3, FB_B4Buck output voltage sense points. Unused regulator can also be used as voltage monitor for an external rail.
J16, J17, J18 LDO1, LDO2, LDO3 LDO output voltage sense points. Unused regulator can also be used as voltage monitor for an external rail.