SLVUCU8 January 2024
Figure 3-2 through Figure 3-5 show the efficiency for both designs on the TPS54KC23EVM. The test points listed in Table 3-3 are used for the efficiency measurement. Use these test points to minimize the contribution of PCB parasitic power loss to the measured power loss.
The following are some additional test setup considerations to minimize external sources of power dissipation.
RELATED IC | TEST POINT NAME | REFERENCE DESIGNATOR | FUNCTION |
---|---|---|---|
U1 | VIN1 | TP1 | Input voltage test point connected near pins of U1 |
PGND1 | TP9 | PGND reference test point for input voltage | |
REG_VOUT1 | TP8 | Output voltage test point near output inductor of U1 | |
REG_GND1 | TP4 | PGND reference test point for output voltage | |
U2 | VIN2 | TP12 | Input voltage test point connected near pins of U2 |
PGND2 | TP24 | PGND reference test point for input voltage | |
REG_VOUT2 | TP20 | Output voltage test point near output inductor of U2 | |
REG_GND2 | TP17 | PGND reference test point for output voltage |