SLVUCV6A May   2024  – November 2024 TPSM81033

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Setup
      1. 2.1.1 Input/Output Connector Descriptions
      2. 2.1.2 Modification
      3. 2.1.3 Input Capacitor
      4. 2.1.4 Output Capacitor
      5. 2.1.5 Feedforward Capacitor
  8. 3Hardware Design Files
    1. 3.1 Schematic
    2. 3.2 PCB Layout
    3. 3.3 Bill of Materials
  9. 4Additional Information
    1. 4.1 Trademarks
  10. 5Revision History

3.2 PCB Layout

The PCB of the TPSM81033EVM has four layers. Figure 3-2 and Figure 3-3 show the top side and bottom side of the PCB layout, respectively. Figure 3-4 and Figure 3-5 show the inner layer 1 and inner layer 2, respectively.

TPSM81033EVM-035 Top-Side Layout Figure 3-2 Top-Side Layout
TPSM81033EVM-035 Bottom-Side Layout Figure 3-3 Bottom-Side Layout
TPSM81033EVM-035 Inner Layer 1 Layout Figure 3-4 Inner Layer 1 Layout
TPSM81033EVM-035 Inner Layer 2 Layout Figure 3-5 Inner Layer 2 Layout