SLVUCX5 May   2024

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Getting Started
      1. 2.1.1 Getting Started: Single EVM
      2. 2.1.2 Getting Started: Multiple EVM Evaluation
    2. 2.2 EVM Details
      1. 2.2.1 Terminal Blocks
      2. 2.2.2 Test Point Descriptions
      3. 2.2.3 Configuration Headers
      4. 2.2.4 Stack-up Headers
      5. 2.2.5 Connectors
      6. 2.2.6 Dip Switches
      7. 2.2.7 EVM Control and GPIO
    3. 2.3 Customization
      1. 2.3.1 Changing the Communication Interface
      2. 2.3.2 Changing the Phase Configuration
  9. 3Software
    1. 3.1 GUI Tool
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  11. 5Additional Information
    1. 5.1 Additional Resources
    2. 5.2 Trademarks

2.2.6 Dip Switches

There are three DIP switches S1, S2, and S3 on the back side of the PCB. S1 and S2 switches allow the user to disconnect the level shifter from the PMIC GPIOs or serial interfaces. The level shifter has pull-ups on the MCU side that can cause unwanted high state on the GPIO signals if configured in high impedance state. S3 switch is used for configuring chip select for target device in multi PMIC/stacked use case. See the Table 3-7 for the descriptions of the switches.

Table 2-7 Dip Switches
SwitchPinSignal Line
S11-16SDA_I2C1/SDI_SPI
2-15SCL_I2C1/SCK_SPI
3-14SDA_I2C2/SDO_SPI
4-13SCL_I2C2/CS_SPI
5-12GPIO1
6-11GPIO2
7-10GPIO3
8-9GPIO4
S21-16GPIO5
2-15GPIO6
3-14GPIO7
4-13GPIO8
5-12GPIO9
6-11GPIO10
7-10Not connected
8-9nINT
S31-12CS5
2-11CS4
3-10CS3
4-9CS2
5-8CS1
6-7GPIO2