SLVUCX5 May   2024

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Getting Started
      1. 2.1.1 Getting Started: Single EVM
      2. 2.1.2 Getting Started: Multiple EVM Evaluation
    2. 2.2 EVM Details
      1. 2.2.1 Terminal Blocks
      2. 2.2.2 Test Point Descriptions
      3. 2.2.3 Configuration Headers
      4. 2.2.4 Stack-up Headers
      5. 2.2.5 Connectors
      6. 2.2.6 Dip Switches
      7. 2.2.7 EVM Control and GPIO
    3. 2.3 Customization
      1. 2.3.1 Changing the Communication Interface
      2. 2.3.2 Changing the Phase Configuration
  9. 3Software
    1. 3.1 GUI Tool
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  11. 5Additional Information
    1. 5.1 Additional Resources
    2. 5.2 Trademarks

2.2.2 Test Point Descriptions

Numerous test points are provided to access voltages and signals. Test points marked with _S are designed for sensing voltages only and are not designed to carry large DC currents.

Table 2-2 Test Point Descriptions
Test Point Device Pin Description
TP1 VCCA_S VCCA voltage sense point. Routed from close to the VCCA pin of the LP8769-Q1.
TP2, TP4, TP6, TP7, TP8, TP9, TP10 GND_S Ground sense points routed from various locations.
TP3 VOUT_LDO_S Voltage sense point for the internal LDO output voltage.
TP5 VIO_S VIO voltage sense routed from the VIO pin of the LP8769-Q1.
TP11, TP12, TP13, TP14, TP15, TP16 GND Solid ground points. Are able to carry larger DC currents.
J14, J16, J17, J19 FB_B1, FB_B2, FB_B3, FB_B4 Buck output voltage sense points. Secondary buck unused FBs are possible to use as voltage monitor as well.