SLVUD40 November 2024 TPS25984B
Table 4-1 lists the TPS25984BEVM eFuse Evaluation Board input and output connectors functionalities. Table 4-2 and Table 4-3 describe the availability of test points and the functionalities of the jumpers. Table 4-4 presents the functions of the signal LEDs.
Connector | Label | Description |
---|---|---|
T1 | VIN (+) | Positive terminal for the input power to the EVM |
T2 | VOUT (+) | Positive terminal for the output power from the EVM |
T3 | PGND (–) | Negative terminal for the EVM (Common for both input and output) |
Test Points | Label | Description |
---|---|---|
TP1 | S1_P | Kelvin sensing points to measure on-resistance: Primary Device (U1) |
TP2 | S1_N | |
TP3 | S2_P | Kelvin sensing points to measure on-resistance: Secondary Device (U2) |
TP4 | S2_N | |
TP5 | VIN | Input Voltage |
TP6 | VOUT | Output Voltage |
TP7 | MODE2 | MODE selection: Secondary Device |
TP8 | FLTb2 | Open-drain active low fault indication: Primary Device |
TP9 | NC/Vinf | Pin 7 from Primary Device |
TP10 | FLTb | Open-drain active low fault indication: Primary Device |
TP11 | D_OC | Open-drain signal to indicate and control power switch ON and OFF status |
TP12 | TEMP | Maximum device die temperature monitor analog voltage output with two (2) TPS25984B eFuses in parallel |
TP13 | DVDT | Start-up output slew rate control |
TP14 | VREG | Internal LDO output from Primary device |
TP15 | IMON | Load current monitor and overcurrent and fast-trip thresholds during steady state |
TP16 | ILIM2 | Current limit and fast-trip threshold during start-up: Secondary Device |
TP17 | ILIM | Current limit and fast-trip threshold during start-up: Primary Device |
TP18 | IREF | Reference voltage for overcurrent and short-circuit protections, and active current sharing blocks |
TP19 | MODE | MODE selection: Primary Device |
TP20 | PG | Open-drain active high power good indication |
TP21 | VREG2 | Internal LDO output from Secondary device |
TP22 | EN | Active high enable input |
TP23 | NC/Vinf2 | Pin 7 from Secondary Device |
TP24 | VDD PULLUP | 5V pullup power supply generated using a LDO from VIN |
TP25 | VCC EXTERNAL | External pullup power supply |
TP26 | GD EXTERNAL | External gate signal for custom load transient |
TP27 | PGND | Supply Ground |
QGND1 | QGND | Device Ground |
G1 | QGND | |
G2 | QGND |
Jumper | Label | Description | Default Jumper Position |
---|---|---|---|
J1 | D_OC | 1-2 Position: The D_OC pull-up supply is generated from VIN using a LDO Through a 100kΩ resistor | 1-2 |
2-3 Position: The D_OC pin is connected to the VREG (internal LDO from the device) of the Primary Device through a 100kΩ resistor | |||
J2 | DVDT | 1-2 Position sets the output slew rate to 1.8V/ms | 5-6 |
3-4 Position sets the output slew rate to 12V/ms | |||
5-6 Position sets the output slew rate to 1.2V/ms | |||
J4 | IMON | 1-2 Position sets the VIMON to 1V at 110A | 1-2 |
3-4 Positionsets the VIMON to 1V at 75A | |||
J5 | ILIM | 1-2 Position sets the inrush current limit to 29A and the active current sharing threshold to 55A with VIREF of 1V: Primary Device | 1-2 |
3-4 Position sets the inrush current limit to 20A and the active current sharing threshold to 38A with VIREF of 1V: Primary Device | |||
J6 | IREF | 1-2 Position sets the reference voltage for overcurrent and short-circuit protection blocks to 1V when testing with two devices or 0.5V when only testing with Primary device | 3-4 |
3-4 Position sets the reference voltage for overcurrent and short-circuit protection blocks to 2V when testing with two devices or 1V when only testing with Primary device | |||
J7 | ILIM2 | 1-2 Position sets the inrush current limit to 29A and the active current sharing threshold to 55A with VIREF of 1V: Secondary Device | 1-2 |
3-4 Position sets the inrush current limit to 20A and the active current sharing threshold to 38A with VIREF of 1V: Secondary Device | |||
J8 | VDD PULL-UP POWER SUPPLY | 1-2 Position provides the VDD pull-up supply from the external power source | 2-3 |
2-3 Position provides the VDD pull-up supply from the onboard 12V to 5V LDO | |||
J9 | EXTERNAL GATE SIGNAL | 1-2 Position provides the GATE signal to the MOSFETs (Q4 – Q6) from the onboard mono-shot | 1-2 |
2-3 Position provides the GATE signal to the MOSFETs (Q4 – Q6) from the external signal generator |
LED | Description |
---|---|
DG1 | When ON, indicates that PG is asserted |
DR1 | When ON, indicates that FLTb is asserted |
DR2 | When ON, indicates that FLTb2 is asserted |