SLWU086C November   2013  – January 2016 ADS42JB46 , ADS42JB49 , ADS42JB69 , DAC38J84

 

  1.   TSW14J56 JESD204B High-Speed Data Capture and Pattern Generator Card User's Guide
    1.     Trademarks
    2. 1 Functionality
      1. 1.1 ADC EVM Data Capture
      2. 1.2 DAC EVM Pattern Generator
    3. 2 Hardware Configuration
      1. 2.1 Power Connections
      2. 2.2 Switches, Jumpers, and LEDs
        1. 2.2.1 Switches and Pushbuttons
        2. 2.2.2 Jumpers
      3. 2.3 LEDs
        1. 2.3.1 Power and Configuration LEDs
        2. 2.3.2 Status LEDs
        3. 2.3.3 Connectors
          1. 2.3.3.1 SMA Connectors
          2. 2.3.3.2 FPGA Mezzanine Card (FMC) Connector
          3. 2.3.3.3 JTAG Connectors
          4. 2.3.3.4 USB I/O Connection
    4. 3 Software Start-Up
      1. 3.1 Installation Instructions
      2. 3.2 USB Interface and Drivers
    5. 4 Downloading Firmware
  2.   Revision History

1.2 DAC EVM Pattern Generator

In pattern generator mode, the TSW14J56EVM generates desired test patterns for DAC EVMs under test. These patterns are sent from the host PC over the USB interface to the TSW14J56. The FPGA stores the data received into the on-board DDR3 memory. The data from the memory is then read by the FPGA, converted to JESD204B serial format, then transmitted to a DAC EVM. The TSW14J56 can generate patterns up to 2G 16-bit samples at a line rate up to 12.5 Gbps.

The GUI comes with several existing test patterns that can be download immediately. The GUI also has a pattern generation tool that allows the user to generate a custom pattern, then download it to the on-board memory. See the High-Speed Data Capture Pro Software User's Guide SLWU087 for more information. Like the ADC capture mode, the DAC pattern generator mode uses .ini files to load predetermined JESD204B interface information to the FPGA.