SLWU087E november 2013 – june 2023
After the board mode has been set, select the device to be tested from the device selection drop-down menu. If the GUI is in ADC mode, clicking on the drop down arrow will display the ADC options available, as shown in Figure 3-26. If in DAC mode, the list will display available DACs. The TSW14J50 device list provides a description of the JESD204B interface in the name itself. For example, if "ADS42JB69_LMF_421" is selected (see Figure 9-2), the interface parameters loaded in the FPGA will set the number of lanes to 4, the number of converters to 2, and the number of octets per frame to 1.