The TI TSW14J58 evaluation module (EVM) is a next-generation pattern generator and data capture card used to evaluate performances of the new TI JESD204C_B device family of high-speed analog-to-digital converters (ADC) and digital-to-analog converters (DAC). For an ADC, by capturing the sampled data over a JESD204C_B interface when using a high-quality, low-jitter clock, and a high-quality input frequency, the TSW14J58 can be used to demonstrate data sheet performance specifications. Using the Xilinx® JESD204C IP core, the TSW14J58 can be dynamically configurable to support lane speeds from 1 Gbps to 24.5 Gbps, from 1 to 16 lanes. Together with the accompanying High-Speed Data Converter Pro Graphic User Interface (GUI), it is a complete system that captures and evaluates data samples from ADC EVMs, generates and sends desired test patterns to DAC EVMs, and perform both tasks at the same time with AFE EVMs (transceiver mode).

The TSW14J58EVM has a single industry standard FMC+ connector that interfaces directly with TI JESD204B ADC, DAC, and AFE EVMs. The FMC+ carrier connector is compatible with the FMC mezzanine connector. When used with an ADC EVM, high-speed serial data is captured, deserialized and formatted by a Xilinx® Kintex® UltraScale® + FPGA. The data is then stored into an external DDR4 memory bank, enabling the TSW14J58 to store up to 1.536G, 16-bit data samples. To acquire data on a host PC, the FPGA reads the data from memory and transmits it on a high-speed 16-bit parallel interface. An onboard high-speed USB 3.0 to parallel converter bridges the FPGA interface to the host PC and GUI.

In pattern generator mode, the TSW14J58 generates the desired test patterns for DAC EVMs under test. These patterns are sent from the host PC over the USB interface to the TSW14J58. The FPGA stores the data received into the board DDR4 memory module. The data from memory is then read by the FPGA and transmitted to a DAC EVM across the FMC+ interface connector. The board contains a 200-MHz oscillator used to generate the DDR4 reference clock and a general purpose clock. shows the TI TSW14J58 evaluation module.

Figure 2-1 TSW14J58EVM

The major features of the TSW14J58 are:

• Backward-compatible with JESD204B (Subclasses: 0 1, 2)
• Support for deterministic latency
• Serial lanes speeds up to 24.5 Gbps
• 16 routed transceiver channels
• 24Gb DDR4 SDRAM (split into two banks of 3 independent 256 × 16, 4Gb SDRAMs). Quarter rate DDR4 controllers supporting up to 1200-MHz operation
• 1.536G of 16-bit samples of onboard memory
• Supports 1.8-V CMOS IO standard for spare FMC+ signals
• General purpose 200-MHz oscillator
• Onboard FTDI FT601Q-B USB 3.0 device for parallel interface to the FPGA
• Onboard FTDI FT4232H USB 2.0 device for FPGA JTAG interface (downloading firmware) and general purpose I/O interface to onboard functions and FMC+
• Reference clocking for transceivers available through FMC+ port or SMAs
• Supported by TI HSDC PRO software
• FPGA firmware developed with Xilinx Vivado development tool.
  • JESD RX IP core with support for:
    • USB and JTAG reconfigurable JESD core parameters: L, M, K, F, HD, S, and more
    • ILA configuration data accessible through USB and JTAG
    • Lane alignment and character replacement enabled or disabled through USB and JTAG
  • JESD TX IP core with support for:
    • USB and JTAG reconfigurable JESD core parameters: L, M, K, F, HD, S, and more
    • ILA configuration data accessible through USB and JTAG
    • Dynamically reconfigurable Transceiver data rate.
  • Serial lane operating range from 1 to 24.5 Gbps

Figure 2-2 shows a block diagram of the TSW14J58 EVM.

Figure 2-2 TSW14J58EVM Block Diagram

New TI high-speed ADCs and DACs now have high-speed serial data that meets the JESD204C_B standard. These devices are generally available on an EVM that connects directly to the TSW14J58EVM. The common connector between the EVMs and the TSW14J58EVM is a Samtec high-speed, high-density FMC+ connector (ASP-184329-01) suitable for high-speed differential pairs up to 32.5 Gbps. A common pinout for the connector across a family of EVMs has been established. At present, the interface between the EVMs and the TSW14J58EVM has defined connections for 32 high-speed differential data pairs (16 RX and 16 TX), 23 single-ended signals, a single-ended SYNC, 5 differential spares, a differential SYNC and SYSREF, and four device clock pairs (FPGA reference clock). The board has 10 spare USB2.0 interface signals, two FPGA reference clock SMAs, three SYNC output SMAs, one external input trigger SMA, four reset switches, and 13 status LEDs.

The data format for JESD204C_B ADCs and DACs is a serialized format, where individual bits of the data are presented on the serial pairs commonly referred to as lanes. Devices designed around the JESD204C_B specification can have up to 16 lanes for transmitting or receiving data. The firmware in the FPGA on the TSW14J58 is designed to accommodate any of TI's ADC or DAC operating with any number of lanes from 1 to 16.

The HSDC Pro GUI loads the FPGA with the appropriate firmware and a specific JESD204C_B configuration, based on the ADC device selected in the device drop down window. Each ADC device that appears in this window has an initialization file (.ini) associated to it. This .ini file contains JESD information, such as number of lanes, number of converters, octets per frame, and other parameters. This information is loaded into the FPGA registers after the user clicks on the capture button. After the parameters are loaded, synchronization is established between the data converter and FPGA and valid data is then captured into the onboard memory. See the High-Speed Data Capture Pro GUI Software User's Guide under the Technical Documents section for more information. Several .ini files are available to allow the user to load predetermined ADC JESD204C_B interfaces.

The TSW14J58 device can capture up to 1.536G 16-bit samples at a maximum line rate of 24 Gbps that are stored inside the onboard DDR4 memory. The data size the user sets in the HSDC Pro GUI must be entered as multiples of 480. To acquire data on a host PC, the FPGA reads the data from memory and transmits parallel data to the onboard high-speed parallel-to-USB3.0 converter.