SNAA365 June   2024 LMK5B33216

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Hardware Architecture
    1. 1.1 Clocking Scheme
    2. 1.2 FPGA Design
  5. 2syn1588® Synchronization Algorithm
    1. 2.1 PTP Time-of-Day Clock Adjustment Algorithm
  6. 3Test Setup
    1. 3.1 FMC Adapter Board
    2. 3.2 Compliance Test Setup
    3. 3.3 Compliance Test of Telecom Profile G.8275.1 - Full Timing Support
      1. 3.3.1 Transfer Characteristic
      2. 3.3.2 Absolute Time Error
      3. 3.3.3 Lock Time
    4. 3.4 Compliance Test of Telecom Profile G.8275.2 - Partial Timing Support
    5. 3.5 Compliance Test of Telecom Profile G.8262.1 - SyncE Transient
  7. 4PTP System Application
  8. 5Additional Development
  9. 6Conclusion
  10. 7References

4 PTP System Application

The PTP clock can be adjusted for 5G wireless applications by applying the same DCO algorithm on the LMK5CxxxxAS1 for DPLL3 as shown in Figure 4-1. The configuration with LMK5CxxxxAS1 is used to achieve the telecommunication accuracy of Class C performance and above while providing the best radio clock jitter performance in the industry, with a maximum jitter of 57fs (12kHz to 20MHz) for 491.52MHz output clocks. With the flexibility provided by the LMK5XXXXXS1 for internal feedback between DPLL and APLL domains, the domains can be cascaded depending on whether a separate PTP domain or separate SyncE domain is required or whether the hybrid PTP and SyncE are combined.

PTP and SyncE for 5G ApplicationsFigure 4-1 PTP and SyncE for 5G Applications