SNAA411 September 2024 CDCLVC1102 , CDCLVC1103 , CDCLVC1104 , CDCLVC1110 , CDCLVD1204 , LMK00301 , LMK00304 , LMK00306 , LMK00308 , LMK01801 , LMK04832 , LMK1C1102 , LMK1C1103 , LMK1C1104 , LMK1C1106 , LMK1C1108 , LMK1D1204 , LMK1D1208 , LMX2485 , LMX2491 , LMX2572 , LMX2592 , LMX2594 , LMX2595 , LMX2820
Applications requiring extremely low phase noise often use OCXO (Oven Controlled Crystal Oscillator) or TCXO (Temperature Compensated Crystal Oscillator) as reference clock in the system. OCXO and TCXO's sinewave output often becomes a bottle neck for slew rate sensitive devices in the clock tree due to fixed amplitude and frequency. Slew rate sensitivity of the subsequent clock devices results in phase noise degradation throughout the clock chain.
There are multiple ways to get around this problem by using external circuity or integrated chips like clock buffers. In this application note, we compare performance improvements in clock trees with TI clock buffer devices with various output format, input power levels and frequencies. This document is to serve as reference to choose the best sine to square wave clock buffer based on application requirements.
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Generally, a clock tree in a system consists of primary reference that is either fanned-out using clock buffers or multiplied / divided through synthesizers (PLL / DPLL) to generate different frequencies. Figure 1-1 shows a generic clock tree of a system containing ADCs, FPGAs or transceivers.
Applications requiring low phase noise requirements that utilizes sine wave reference are found in medical, communication, T&M and A&D systems. For example, radars are dependent on low phase noise to detect one or more objects accurately.
Additive phase noise gradually adds up with each device in the clock tree. Good system design practices are crucial to avoid any additional degradation. One of those consideration is due to the input slew rate and amplitude requirements for different devices when converting sine wave to logic levels.
Slew rate of sine wave is dependent on frequency of operation and voltage of signal. Complying with input slew rate requirement for clock devices is necessary to provide certain phase noise performance.
To imporve phase noise of clock devices, higher slew input is recommended. Most vendors have this recommendation outlined in the data sheet for buffer, synthesizer, and jitter cleaners.
Slew rate of sine wave input signal can be changed by increasing/decreasing frequency or voltage as shown in Equation 1.
Both of these variables cannot be controlled when using a fixed output amplitude and frequency source which often is the case for systems using OCXO/TCXOs.
Current approaches to solve slew rate sensitivity problem use additional circuitry is input of clock devices that takes additional space on the board. The overall system becomes costly and dependency of multiple discrete components also adds complexity in design. Furthermore, using an amplifier or comparator stage adds noise in the subsequent clock tree because amplifier or comparators are usually not optimized for phase noise performance like clock buffers. Figure 3-1 shows a generalized version of current approach without clock buffers. A better approach is to use integrated chip like clock buffer which has all the required circuity to amplify slow slew rates signals and optimized for all clocking parameters. Clock buffer converts the slow slew rate inputs to logic levels with very low additive phase noise, thus boosting the signal slew rate to also minimize phase noise degradation though the device in clock tree. Also, clock buffers reduces external BOM (bill of materials) depending on different features like internal biasing and AC coupling mode, and so on.
TI has a wide portfolio of clock buffers that support sine wave input for single ended, differential and configurable buffers. TI clock buffers covers all the logic levels from LVCMOS (LMK1C110x), LVDS (LMK1D1xxx), LVPECL (CDCLVP12xx), and Universal buffers that support all industry standard output and inputs formats (LMK0030x, LMK01000, CDCLVC1310). This application note specifically uses LMK1C110x family of buffers for performance measurements due to inherent low additive phase noise.
While using the clock buffer as sine to square wave conversion, make sure to consider specific input VOH, VOL, VOD, input common mode, AC coupled inputs and internal or external biasing requirements of each clock buffer.
In the following sections, most commonly used input interface, external or internal biasing tips are discussed for TI buffers. Since the input architecture for different generation of buffers get improvements over time. There are subtle differences to keep in mind interfacing clock signal to the input of each buffer.
There are two major buffer input stages, single ended (LVCMOS) or differential (LVDS, LVPECL, CML, LP-HCSL, HCSL, HTSL). The differential inputs can be standard specific or universal inputs. Universal inputs accept all the supported standard input driver interface.
Differential inputs can also be used as single ended input. Inverting or non-inverting input is selected as reference clock input and the other input is DC biased to the mid point reference clock input. Both clock reference and DC biased inputs are set within the input swing and common mode range requirements of each device.
In the following sections, we discuss internal or external DC bias use, single ended input and differential input re-bias techniques across different TI clock buffer families.
Generally, TI differential clock buffer families have two different DC biasing options, internal bias with small DC offset or internal DC bias with hysteresis. Both DC bias options are used to set the outputs to low state and avoid glitches on the outputs when there is loss of signal or clock. Figure 4-1 and Figure 4-2 shows both biasing techniques.
Things to consider before opting for internal and external DC bias.