10.5.1.1 Design Requirements
Clocks outputs:
- 1x 245.76-MHz clock for JESD204B ADC, LVPECL.
- This clock requires the best performance in this example.
- 2x 983.04-MHz clock for JESD204B DAC, LVPECL.
- 1x 122.88-MHz clock for JESD204B FPGA block, LVDS
- 4x 10.24-MHz SYSREF for ADC (LCPECL), DAC (LVPECL), FPGA (LVDS).
- 2x 122.88-MHz clock for FPGA, LVDS
For best performance, the highest possible phase detector frequency is used at PLL2. As such, a 122.88-MHz VCXO is used.