SNAS605AS March 2013 – May 2020 LMK04821 , LMK04826 , LMK04828
PRODUCTION DATA.
The device clocks include both a analog and digital delay for phase adjustment of the clock outputs.
The analog delay allows a nominal 25-ps step size, and range from 0 to 575 ps of total delay. Enabling the analog delay adds a nominal 500 ps of delay, in addition to the programmed value.
The digital delay allows a group of outputs to be delayed from 4 to 32 VCO cycles. The delay step can be as small as half the period of the clock distribution path. For example, a 2-GHz VCO frequency results in 250 ps coarse tuning steps. The coarse (digital) delay value takes effect on the clock outputs after a SYNC event.
There are two ways to use the digital delay.