SNAS654 Data sheet

SNAS654A March 2015 – July 2016 LMX2571

PRODUCTION DATA.

7 Detailed Description

7.1 Overview

The LMX2571 is a frequency synthesizer with low-noise, high-performance integrated VCOs. The 5-GHz VCO cores, together with the output channel dividers, can produce frequencies from 10 MHz to 1344 MHz. The LMX2571 supports two operation modes, synthesizer mode and PLL mode. In synthesizer mode, the entire device is utilized; in PLL mode the internal VCO is bypassed, and an external VCO is required to implement a complete synthesizer.

The reference clock input supports a crystal used for the on-chip oscillator, AC-coupled differential clock signals, and DC-coupled single-ended clock signals such as XO or CMOS clock devices.

The PLL is a fractional-N PLL with programmable Delta Sigma modulator (first order to fourth order). The fractional denominator is of variable length and up to 24-bits long, providing a frequency step with very fine resolution.

The internal VCO can be bypassed, allowing the use of an external VCO. A separate 5-V charge pump is dedicated for the external VCO, eliminating the need for an op-amp to support 5-V VCOs. A new advanced FastLock technique is developed to shorten the lock time to less than 1.5 ms, even there is a very narrow loop bandwidth.

A unique programmable multiplier is incorporated in the R-divider. The multiplier is used to avoid and reduce integer boundary spurs or to increase the phase detector frequency for higher performance.

The LMX2571 supports direct digital FSK modulation, thus allowing a change in the output frequency by changing the N-divider value. The N-divider value can be programmed through MICROWIRE interface or through pins. Discrete 2-, 4- and 8-level FSK, as well as arbitrary-level FSK, are supported. Arbitrary-level FSK can be used to construct pulse-shaping FSK or analog-FM modulation.

The output has an integrated T/R switch, and the divided-down internal or external VCO signal can be output to either the TX port or the RX port. The switch can also be configured as a 1:2 fanout buffer, providing the signal on both outputs at the same time. In addition to port switching, the output frequency can be switched between two pre-defined frequencies, F1 and F2, simultaneously. This feature is ideal for use in FDD duplex system where the TX frequency is different from RX (LO) frequency.

The LMX2571 requires only a single 3.3-V power supply. Digital logic interface is 1.8-V input compatible. The analog blocks power supplies use integrated LDOs, eliminating the need for high performance external LDOs.

Programming of the device is achieved through the MICROWIRE interface. The device can be powered down through a register programming or toggling the Chip Enable (CE) pin.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Reference Oscillator Input

The OSCin and OSCin* pins are used as frequency reference inputs to the device. The OSCin pin can be driven single-ended with a CMOS clock or a crystal oscillator. The on-chip crystal oscillator can also be used with an external crystal as the reference clock. Differential clock input is also supported, making it easily to interface with high performance system clock devices such as TI’s LMK series clock devices.

Because the OSCin or OSCin* signal is used as a clock for VCO calibration, a proper signal needs to be applied at the OSCin and/or OSCin* pin at the time of programming the R0 register. A higher slew rate tends to yield the best fractional spurs and phase noise, so a square wave signal is best for the OSCin and/or OSCin*pins. If using a sine wave, higher frequencies tend to yield better phase noise and fractional spurs due to their higher slew rates.

7.3.2 R-Dividers and Multiplier

The R-divider consists of a Pre-divider, a Multiplier (MULT), and a Post-divider.

Figure 14. R-Divider

Both the Pre- and Post-dividers divide frequency down while the MULT multiplies frequency up. The purpose of adding a multiplier is to avoid and reduce integer boundary spurs or to increase the phase-detector frequency for higher performance. See MULT Multiplier for details. The phase detector frequency, f_PD, is therefore equal to

Equation 1. f_PD = (f_OSCin / Pre-divider) * (MULT / Post-divider)

When using the Multiplier (MULT > 1), there are some points to remember:

The Multiplier must be greater than the Pre-divider.
Crystal mode must be disabled (XTAL_EN=0).
Using the multiplier may add noise, especially for multiplier values greater than 6.

7.3.3 PLL Phase Detector and Charge Pump

The phase detector compares the outputs of the Post-divider and N-divider and generates a correction current corresponding to the phase error. This charge pump current is programmable to different strengths.

7.3.4 PLL N-Divider and Fractional Circuitry

The total N-divider value is determined by N_integer + NUM / DEN. The N-divider includes fractional compensation and can achieve any fractional denominator (DEN) from 1 to 16,777,215 (2²⁴ – 1). The integer portion, N_integer, is the whole part of the N-divider value and the fractional portion, N_frac = NUM / DEN, is the remaining fraction. N_integer, NUM and DEN are programmable.

The order of the delta sigma modulator is also programmable from integer mode to fourth order. There are several dithering modes that are also programmable. Dithering is used to reduce fractional spurs. In order to make the fractional spurs consistent, the modulator is reset any time that the R0 register is programmed.

7.3.5 Partially Integrated Loop Filter

The LMX2571 integrates the third and fourth pole of the loop filter. The values for the resistors can be programmed independently through the MICROWIRE interface. The larger the values of the resistors, the stronger the attenuation of the internal loop filter. This partially integrated loop filter can only be used in synthesizer mode.

Figure 15. Integrated Loop Filter

7.3.6 Low-Noise, Fully Integrated VCO

The LMX2571 includes a fully integrated VCO. The VCO generates a frequency which varies with the tuning voltage from the loop filter. Output of the VCO is fed to a prescaler before going to the N-divider. The prescaler value is selectable between 2 and 4. In general, prescaler equals 2 will result in better phase noise especially when the PLL is operated in fractional-N mode. If the prescaler equals 4, however, the device will consume less current. The VCO frequency is related to the other frequencies and Prescaler as follows:

Equation 2. f_VCO = f_PD * N-divider * Prescaler

In order to reduce the VCO tuning gain, thus improving the VCO phase noise performance, the VCO frequency range is divided into several different frequency bands. This creates the need for frequency calibration in order to determine the correct frequency band given a desired output frequency. The VCO is also calibrated for amplitude to optimize phase noise. These calibration routines are activated any time that the R0 register is programmed with the FCAL_EN bit equals one. It is important that a valid OSCin signal must present before VCO calibration begins.

This device will support a full sweep of the valid temperature range of 125°C (–40°C to 85°C) without having to re-calibrate the VCO. This is important for continuous operation of the synthesizer under the most extreme temperature variation.

7.3.7 External VCO Support

The LMX2571 supports an external VCO in PLL mode. In PLL mode, the internal VCO and its associated charge pump are powered down, and a 5-V charge pump is switched in to support external VCO. No extra external low noise op-amp is required to support 5-V tuning range VCO. The external VCO output can be obtained directly from the VCO or from the device’s RF output buffer.

7.3.8 Programmable RF Output Divider

The internal VCO RF output divider consists of two sub-dividers; the total division value is equal to the multiplication of them. As a result, the minimum division is 4 while the maximum division is 448.

Figure 16. VCO Output Divider

There is only one output divider when external VCO is being used. This divider supports even and odd division, and its values are programmable between 1 and 10.

7.3.9 Programmable RF Output Buffer

The RF output buffer type is selectable between push-pull and open drain. If open drain buffer is selected, external pullup to VccIO is required. Regardless of output type, output power can be programmed to various levels. The RF output buffer can be disabled while still keeping the PLL in lock. See RF Output Buffer Type for details.

7.3.10 Integrated TX, RX Switch

The LMX2571 integrates a T/R switch which is controlled by the TrCtl pin. The output from the internal VCO or external VCO divider will be routed to either the RFoutTx or RFoutRx ports, depending on the state of the TrCtl pin. The TrCtl pin not only controls the output port, but may also switch the output frequency simultaneously. For example, if TrCtl = 1, the active port is RFoutTx with an output frequency of F1. When TrCtl changes from 1 to 0, the active port could be RFoutRx with an output frequency of F2. LMX2571 has two sets of register to store the configurations for F1 and F2.

The T/R switch could also be configured as a fanout buffer to output the same signal at both RFoutTx and RFoutRx ports at the same time. All of these features are also programmable, see Programming and Frequency and Output Port Switching with TrCtl Pin for details.

7.3.11 Powerdown

The LMX2571 can be powered up and down using the CE pin or the POWERDOWN bit. All registers are preserved in memory while it is powered down. When the device comes out of the powered down state, either by resuming the POWERDOWN bit to zero or by pulling back CE pin HIGH (if it was powered down by CE pin), it is required that register R0 with FCAL_EN=1 be programmed again to re-calibrate the device.

7.3.12 Lock Detect

The MUXout pin of the LMX2571 can be configured to output a signal that indicates when the PLL is being locked. If lock detect is enabled while the MUXout pin is configured as a lock-detect output, when the device is locked the MUXout pin output is a logic HIGH voltage. When the device is unlocked, MUXout output is a logic LOW voltage.

7.3.13 FSK Modulation

Direct digital FSK modulation is supported in LMX2571. FSK modulation is achieved by changing the output frequency by changing the N-divider value. The LMX2571 supports four different types of FSK operation.

FSK PIN mode. LMX2571 supports 2-, 4- and 8-level FSK modulation in PIN mode. In this mode, symbols are directly fed to the FSK_D0, FSK_D1, and FSK_D2 pins. Symbol clock is fed to the FSK_DV pin. Symbols are latched into the device on the rising edge of the symbol clock. The maximum supported symbol clock rate is 1 MHz. The device has eight dedicated registers to pre-store the desired FSK frequency deviations, with each register corresponding to one of the FSK symbols. The LMX2571 will change its output frequency according to the states on the FSK pins; no extra register programming is required.
FSK SPI mode. This mode is identical to the FSK PIN mode with the exception that the control for the selected FSK level is not performed with external pins but with register R34. Each time when register R34 is programmed, change only the FSK_DEV_SEL field to select the desired FSK frequency deviation as stored in the dedicated registers.
FSK SPI FAST mode. In this mode, instead of selecting one of the pre-stored FSK level, change the FSK deviation directly by writing to the register R33, FSK_DEV_SPI_FAST field. As a result, this mode supports arbitrary-FSK level, which is useful to construct pulse-shaping or analog-FM modulation.
FSK I2S mode. This mode is similar to the FSK SPI FAST mode, but the programming format is an I2S format on dedicated pins instead of SPI. The benefit of using I2S is that this interface could be shared and synchronous to other digital audio interfaces. The same FSK data input pins that are used in FSK PIN mode are re-used to support I2S programming. In this mode only the 16 bits of DATA field is required to program. The data is transmitted on the high or low side of the frame sync (programmable in register R34, FSK_I2S_FS_POL). The unused side of the frame sync needs to be at least one clock cycle. In other words, 17 (16 + 1) CLK cycles are required at a minimum for one I2S frame. Maximum I2S clock rate is 100 MHz.

Figure 17. FSK PIN Mode Timing

Figure 18. FSK I2S Mode Timing

See Direct Digital FSK Modulation for FSK operation details.

7.3.14 FastLock

The LMX2571 includes a FastLock feature that can be used to improve the lock times in PLL mode when the loop bandwidth is small. In general, the lock time is approximately equal to 4 divided by the loop bandwidth. If the loop bandwidth is 1 kHz, then the lock time would be 4 ms. However, if the f_PD is much higher than the loop bandwidth, cycle slipping may occur, and the actual lock time will be much longer. Traditional fastlock usually reduces lock time by increasing loop bandwidth during frequency switching. However, there is a limitation on the achievable maximum loop bandwidth due to limitation on charge-pump current and loop filter component values. In some cases, this kind of fastlock technique will make cycle slip even worse.

The LMX2571 adopts a new FastLock approach that eliminates the cycle slip problem. With an external analog SPST switch in conjunction with LMX2571’s FastLock control, the lock time for a 100-MHz frequency switch could be settled in less than 1.5 ms. See FastLock with External VCO for details.

7.3.15 Register Readback

The LMX2571 allows any of its registers to be read back. The MUXout pin can be programmed to support either lock-detect output or register-readback serial-data output. To read back a certain register value, follow the following steps:

Set the R/W bit to 1; the data field contents are ignored.
Send the register to the device; readback serial data will be output starting at the 9^th clock cycle.

Figure 19. Register Readback Timing Diagram

7.4 Device Functional Modes

7.4.1 Operation Mode

The device can be operated in synthesizer mode or PLL mode.

Synthesizer mode. The internal VCO will be adopted.
PLL mode. The device is operated as a standalone PLL; an external VCO is required to complete the loop.

7.4.2 Duplex Mode

LMX2571 supports fast frequency switching between two pre-defined register sets, F1 and F2. This feature is good for duplex operation. The device supports three duplex modes:

Synthesizer duplex mode. Both F1 and F2 are operated in synthesizer mode.
PLL duplex mode. Both F1 and F2 are operated in PLL mode.
Synthesizer/PLL duplex mode. In this mode, F1 and F2 will be operated in different operation mode.

7.4.3 FSK Mode

LMX2571 supports four direct digital FSK modulation modes.

FSK PIN mode. 2-, 4- and 8-level FSK modulation. Modulation data is fed to the device through dedicated pins.
FSK SPI mode. 2-, 4- and 8-level FSK modulation. Pre-defined FSK deviation is selected through SPI programming.
FSK SPI FAST mode. This mode supports arbitrary-level FSK modulation. Desired FSK deviation is written to the device through SPI programming.
FSK I2S mode. Arbitrary-level FSK modulation is supported. Desired FSK deviation is fed to the device through dedicated pins.

7.5 Programming

The LMX2571 is programmed using several 24-bit registers. A 24-bit shift register is used as a temporary register to indirectly program the on-chip registers. The shift register consists of a data field, an address field, and a R/W bit. The MSB is the R/W bit. 0 means register write while 1 means register read. The following 7 bits, ADDR[6:0], form the address field which is used to decode the internal register address. The remaining 16 bits form the data field DATA[15:0]. While LE is low, serial data is clocked into the shift register upon the rising edge of clock. Serial data is shifted MSB first into the shift register when programming. When LE goes high, data is transferred from the data field into the selected active register bank. See Figure 1 for timing diagram details.

7.5.1 Recommended Initial Power on Programming Sequence

When the device is first powered up, it needs to be initialized, and the ordering of this programming is important. The sequence is listed below. After this sequence is completed, the device should be running and locked to the proper frequency.

Apply power to the device and ensure the Vcc pins are at the proper levels.
If CE is LOW, pull it HIGH.
Wait 100 µs for the internal LDOs to become stable.
Ensure that a valid reference is applied to the OSCin pin.
Program register R0 with RESET=1. This will ensure all the registers are reset to their default values.
Program in sequence registers R60, R58, R53, …, R1 and then R0.

7.5.2 Recommended Sequence for Changing Frequencies

The recommended sequence for changing frequencies in different scenarios is as follows:

If the N-divider is changing, program the relevant registers, then program R0 with FCAL_EN = 1.
In FSK SPI mode, FSK SPI FAST mode, and FSK I2S mode, the fractional numerator is changing; program the relevant registers only.
If switching frequency between F1 and F2, program the relevant control registers only or toggle the TrCtl pin. See Frequency and Output Port Switching with TrCtl Pin for details.

7.6 Register Maps

REG.	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	POR
REG.	R/W	ADDRESS[6:0]							DATA[15:0]
R60	R/W	0	1	1	1	1	0	0	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	3C4000h
R58	R/W	0	1	1	1	0	1	0	1	0	0	0	1	1	0	0	0	0	0	0	0	0	0	0	3A0C00h
R53	R/W	0	1	1	0	1	0	1	0	1	1	1	1	0	0	0	0	0	0	0	0	1	1	0	352802h
R47	R/W	0	1	0	1	1	1	1	0	DITHERING		0	0	0	0	0	0	0	0	0	0	0	0	0	2F0000h
R46	R/W	0	1	0	1	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	1	VCO_ SEL_ STRT	VCO_SEL		2E001Ah
R42	R/W	0	1	0	1	0	1	0	0	0	0	0	0	0	1	0	0	0	EXTVCO _CP _POL	EXTVCO_CP_IDN					2A0210h
R41	R/W	0	1	0	1	0	0	1	0	0	0	0	EXTVCO_CP_IUP					EXTVCO_CP_GAIN		CP_IDN					290810h
R40	R/W	0	1	0	1	0	0	0	0	0	0	CP_IUP					CP_GAIN		0	1	1	1	0	0	28101Ch
R39	R/W	0	1	0	0	1	1	1	0	0	0	1	0	0	0	1	1	1	1	1	SDO_LD_ SEL	0	1	LD_EN	2711F0h
R35	R/W	0	1	0	0	0	1	1	0	0	MULT_WAIT											OUTBUF _AUTO MUTE	OUTBUF _TX _TYPE	OUTBUF _RX _TYPE	230647h
R34	R/W	0	1	0	0	0	1	0	IPBUF DIFF_ TERM	IPBUF_ SE_DIFF _SEL	XTAL_PWRCTRL			XTAL_EN	0	FSK_I2S_ FS_POL	FSK_I2S_ CLK_POL	FSK_LEVEL		FSK_DEV_SEL			FSK_ MODE_ SEL0	FSK_ MODE_ SEL1	221000h
R33	R/W	0	1	0	0	0	0	1	FSK_DEV_SPI_FAST																210000h
R32	R/W	0	1	0	0	0	0	0	FSK_DEV7_F2																200000h
R31	R/W	0	0	1	1	1	1	1	FSK_DEV6_F2																1F0000h
R30	R/W	0	0	1	1	1	1	0	FSK_DEV5_F2																1E0000h
R29	R/W	0	0	1	1	1	0	1	FSK_DEV4_F2																1D0000h
R28	R/W	0	0	1	1	1	0	0	FSK_DEV3_F2																1C0000h
R27	R/W	0	0	1	1	0	1	1	FSK_DEV2_F2																1B0000h
R26	R/W	0	0	1	1	0	1	0	FSK_DEV1_F2																1A0000h
R25	R/W	0	0	1	1	0	0	1	FSK_DEV0_F2																190000h
R24	R/W	0	0	1	1	0	0	0	0	0	0	0	0	FSK_EN_ F2	EXTVCO_CHDIV_F2				EXTVCO _SEL _F2	OUTBUF_TX_PWR_F2					180010h
R23	R/W	0	0	1	0	1	1	1	0	0	0	OUTBUF_RX_PWR_F2					OUTBUF _TX_EN _F2	OUTBUF _RX_EN _F2	0	0	0	LF_R4_F2			1710A4h
R22	R/W	0	0	1	0	1	1	0	LF_R3_F2			CHDIV2_F2			CHDIV1_F2		PFD_DELAY_F2			MULT_F2					168584h
R21	R/W	0	0	1	0	1	0	1	PLL_R_F2								PLL_R_PRE_F2								150101h
R20	R/W	0	0	1	0	1	0	0	PLL_N_ PRE_F2	FRAC_ORDER_F2			PLL_N_F2												140028h
R19	R/W	0	0	1	0	0	1	1	PLL_DEN_F2[15:0]																130000h
R18	R/W	0	0	1	0	0	1	0	PLL_NUM_F2[15:0]																120000h
R17	R/W	0	0	1	0	0	0	1	PLL_DEN_F2[23:16]								PLL_NUM_F2[23:16]								110000h
R16	R/W	0	0	1	0	0	0	0	FSK_DEV7_F1																100000h
R15	R/W	0	0	0	1	1	1	1	FSK_DEV6_F1																F0000h
R14	R/W	0	0	0	1	1	1	0	FSK_DEV5_F1																E0000h
R13	R/W	0	0	0	1	1	0	1	FSK_DEV4_F1																D0000h
R12	R/W	0	0	0	1	1	0	0	FSK_DEV3_F1																C0000h
R11	R/W	0	0	0	1	0	1	1	FSK_DEV2_F1																B0000h
R10	R/W	0	0	0	1	0	1	0	FSK_DEV1_F1																A0000h
R9	R/W	0	0	0	1	0	0	1	FSK_DEV0_F1																90000h
R8	R/W	0	0	0	1	0	0	0	0	0	0	0	0	FSK_EN_ F1	EXTVCO_CHDIV_F1				EXTVCO _SEL _F1	OUTBUF_TX_PWR_F1					80010h
R7	R/W	0	0	0	0	1	1	1	0	0	0	OUTBUF_RX_PWR_F1					OUTBUF _TX_EN _F1	OUTBUF _RX_EN _F1	0	0	0	LF_R4_F1			710A4h
R6	R/W	0	0	0	0	1	1	0	LF_R3_F1			CHDIV2_F1			CHDIV1_F1		PFD_DELAY_F1			MULT_F1					68584h
R5	R/W	0	0	0	0	1	0	1	PLL_R_F1								PLL_R_PRE_F1								50101h
R4	R/W	0	0	0	0	1	0	0	PLL_N_ PRE_F1	FRAC_ORDER_F1			PLL_N_F1												40028h
R3	R/W	0	0	0	0	0	1	1	PLL_DEN_F1[15:0]																30000h
R2	R/W	0	0	0	0	0	1	0	PLL_NUM_F1[15:0]																20000h
R1	R/W	0	0	0	0	0	0	1	PLL_DEN_F1[23:16]								PLL_NUM_F1[23:16]								10000h
R0	R/W	0	0	0	0	0	0	0	0	0	RESET	POWER DOWN	RXTX_ CTRL	RXTX_ POL	F1F2_ INIT	F1F2_ CTRL	F1F2_ MODE	F1F2_ SEL	0	0	0	0	1	FCAL_EN	3h

The POR value is the power-on reset value that is assigned when the device is powered up or the RESET bit is asserted. POR is not a default working mode, all registers are required to program properly in order to make the device works as desired.