SNAU273 December   2022 LMX2820

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2SYNC Category
  5. 3SYNC Examples
    1. 3.1 Category 1 SYNC Example
    2. 3.2 Category 2 SYNC Example
    3. 3.3 Category 3 SYNC Example
  6. 4Other Considerations When Using SYNC
  7. 5References

3 SYNC Examples

In the following sections, we can see how to synchronize the outputs from two LMX2820 devices. Below is the block diagram of the test setup.

Figure 3-1 Test Setup

The LMK04832 is operated in Single Loop Mode. That is, PLL1 is not used. PLL2 takes the 100-MHz input clock to lock the VCO. Output from the VCO is divided down to 100 MHz, which is used as the reference clock of the LMX2820. SYSREF of the LMK04832 is used to generate a time-critical SYNC pulse for Category 3 SYNC.

The LMK04832 is able to phase align all of the output clocks. All the clocks and SYNC pulses are phase-aligned before feeding them to the LMX2820 devices.

Figure 3-2 LMK04832 Configuration

The output channel-to-channel skew of the LMK04832 is around 100 ps. As such, the two 100-MHz clocks are not exactly in phase. This skew is eventually carried forward to the output of the LMX2820 devices. For better illustration purpose, the data in the following sections has this skew written off.