The ADC128S102EVM has provisions to drive all eight analog input channels, the external power supply, and the connection to the precision host interface (PHI) motherboard to communicate with the user-friendly GUI. These section are outlined in red in Figure 1-1. The final section is the EEPROM section below the J25 PHI connector. The switch, S1, must be in the WR_DIS position and must not be changed.

Table 1-1 lists the related documents that are associated with the ADC128S102EVM.

The EVM board has two subminiature version A (SMA) connectors, with six other footprints to populate the remaining SMA connectors (if required) to connect to the eight analog input channels. Shunt headers are also available in parallel with each respective SMA connector. As shown in Figure 1-2, each shunt header is connected to an analog input channel of the ADC128S102 through an operational amplifier (op amp) driver circuit. An input circuit is connected to each ADC analog input. The driver circuit consists of an initial RC circuit for noise filtering, followed by an OPA2320 (a dual-channel op amp configured, by default, as a buffer). The board has provisions to change the buffer circuit configuration, by removing the 0-Ω resistor and adding the desired RC combination. At the output of each op amp, is a 3-pin header that provides the option to bypass the buffer.