SNAU287 November 2023
- 1
- Description
- Features
- 4
- 1Evaluation Module Overview
- 2Hardware
- 3Software
- 4Hardware Design Files
- 5Additional Information
- 6Related Documentation
2.2.2 Configuring the Control Pins
The LMK3H0102 has multiple external control pins to configure the operating mode and initial settings on POR. Figure 3-3 shows how the LMK3H0102 control pins can be configured through the jumpers.
Figure 2-3 LMK3H0102EVM Control
JumpersThe REF_CTRL, OE, OTP_SEL0/SCL, and OTP_SEL1/SDA pins are all two level pins, and can be pulled high or low through the jumpers. Additionally, the REF_CTRL and OE pins can be controlled through software via TICS Pro to set the pin voltage.
The FMT_ADDR pin can be connected to VDD, GND, SCL, or SDA, in addition to being controllable via software - all of these options are available using the J5 jumper.
The LMK3H0102 control pins perform different functions depending on the mode of operation.
For OTP Mode, refer to Table 3-2 for jumper descriptions.
For I2C Mode, refer to Table 3-3 for jumper descriptions.
| Component | Name (type) | Description | |
|---|---|---|---|
| J1 | REF_CTRL (2-level input) | REF_CTRL Pin REF_CTRL state is sampled on POR and determines the mode of operation. | |
| REF_CTRL State | Operating Mode | ||
HI: Tie pins 1 & 2 | OTP Mode OTP_SEL0 and OTP_SEL1 pins are sampled on start-up to determine the OTP page to load | ||
LO: Tie pins 5 & 6 Floating (Default) | I2C Mode FMT_ADDR pin is sampled on the first I2C transaction to determine the I2C address of the device | ||
| SW: Tie pins 3 & 4 | Pin state is controlled by software. This option can be used when using an external VDD source to set the pin state through TICS Pro to switch between I2C Mode and OTP Mode on power cycle quickly | ||
| J2 | OE (2-level input) | OE Pin The OE pin controls the output enable, and has the same function regardless of start-up mode. The default behavior of the pin is active-low; this can be changed to active-high in the Wizard. | |
| OE State | Operating Mode | ||
HI: Tie pins 1 & 2 | Disable the clock outputs. | ||
LO: Tie pins 5 & 6 (Default) | Enable the clock outputs. If the clock outputs are disabled in software, the outputs remain disabled. | ||
| SW: Tie pins 3 & 4 | Pin state is controlled by software | ||
| J3 & J4 | OTP_SEL0 | OTP_SEL0 Pin The OTP_SEL0 and OTP_SEL1 pins control the OTP page loaded from the EFUSE into the active device registers on startup. | |
OTP_SEL1 OTP_SEL0 | OTP Page | ||
LO: Tie J7 pins 2 & 3 LO: Tie J3 pins 2 & 3 | |||
LO: Tie J7 pins 2 & 3 HI: Tie J3 pins 1 & 2 | |||
HI: Tie J7 pins 1 & 2 LO: Tie J3 pins 2 & 3 | |||
HI: Tie J7 pins 1 & 2 HI: Tie J3 pins 1 & 2 | |||
Connect J7 pin 2 to J6 (Default) Connect J3 pin 2 to J4 (Default) | Pulled high through resistors. | ||
| J5 | FMT_ADDR | FMT_ADDR Pin The FMT_ADDR pin is ignored by default in LMK3H0102V33 default configuration. Devices with custom configurations can be populated where R9[8] = 1. In this case, the FMT_ADDR pin sets the output format for OUT[1:0]. | |
| FMT_ADDR State | Output Format | ||
HI: Tie J5 pins 1 & 2 (Default) | LP-HCSL 85-Ω Termination | ||
| LO: Tie J5 pins 9 & 10 | LP-HCSL 100-Ω Termination | ||
| Software: Tie J5 pins 7 & 8 | Pulled to HI or LO using TICS Pro | ||
| OTP_SEL0: Tie J5 pins 3 and 4 | Matches state of OTP_SEL0 pin | ||
| OTP_SEL1: Tie J5 pins 5 and 6 | Matches state of OTP_SEL1 pin | ||
| J6 & J7 | OTP_SEL1 | OTP_SEL1 Pin See OTP_SEL0 Pin | |
| J22 | LVL_SFT | Tie J22 pins 2 & 3 together in OTP Mode. | |
| Component | Name (type) | Description | |
|---|---|---|---|
| J1 | REF_CTRL (2-level input) | REF_CTRL Pin REF_CTRL state is sampled on POR and determines the mode of operation. | |
| REF_CTRL State | Operating Mode | ||
HI: Tie pins 1 & 2 | OTP Mode OTP_SEL0 and OTP_SEL1 pins are sampled on start-up to determine the OTP page to load | ||
LO: Tie pins 5 & 6 Floating (Default, internal pulldown resistor) | I2C Mode FMT_ADDR pin is sampled on the first I2C transaction to determine the I2C address of the device | ||
| SW: Tie pins 3 & 4 | Pin state is controlled by software This option can be used when using an external VDD source to set the pin state through TICS Pro to switch between I2C Mode and OTP Mode on POR quickly | ||
| J2 | OE (2-level input) | OE Pin The OE pin controls the output enable, and has the same function regardless of start-up mode. The default behavior of the pin is active-low; this can be changed via software to active-high. | |
| OE State | Operating Mode | ||
HI: Tie pins 1 & 2 | Disable the clock outputs. | ||
LO: Tie pins 5 & 6 (Default) | Enable the clock outputs. If the clock outputs are disabled in software, the outputs remain disabled. | ||
| SW: Tie pins 3 & 4 | Pin state is controlled by software | ||
| J3 & J4 | SCL | SCL Pin The SCL and SDA pins control the I2C interface of the device. If VDD is 1.8 V, then use J22 to level-shift the logic high voltage down to 1.65 V to prevent device damage. SCL is the I2C clock, and SDA is the I2C data. | |
|
SCL SDA | I2C Configuration | ||
|
Connect J3 pin 2 to J4 (Default) Connect J7 pin 2 to J6 (Default) |
SCL connected to the USB2ANY SDA connected to the USB2ANY | ||
All other states | I2C disconnected | ||
| J5 | FMT_ADDR | FMT_ADDR Pin In I2C mode, the I2C address is latched based on the state of the FMT_ADDR pin at the first I2C transaction. | |
| FMT_ADDR State | I2C Address | ||
HI: Tie J5 pins 1 & 2 (default) | 0x69 | ||
| LO: Tie J5 pins 9 & 10 | 0x68 | ||
| SCL: Tie J5 pins 3 and 4 | 0x6A | ||
| SDA: Tie J5 pins 5 and 6 | 0x6B | ||
| SW: Tie J5 pins 7 and 8 | I2C address controlled by software, latched on first I2C transaction | ||
| J6 & J7 | SDA | SDA Pin See SCL Pin | |
| J22 | LVL_SFT | I2C Level Shift Pin The state of this pin determines whether or not the I2C level shifter is enabled. R6 and R9 are depopulated by default. | |
| LVL_SFT State | Level Shift Operation | ||
HI: Tie J22 pins 1 and 2 (Default) | Level shifter is active | ||
LO: Tie J22 pins 2 and 3 together | Level shifter is inactive R6 and R9 must be populated | ||