SNAU288 December   2023 LMX1906-SP

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Setup
      1. 2.1.1 Evaluation Setup Requirement
      2. 2.1.2 Connection Diagram
        1. 2.1.2.1 How to Enable Full SPI Control
      3. 2.1.3 Power Requirements
      4. 2.1.4 Pin Mode Strapping
      5. 2.1.5 Reference Clock
        1. 2.1.5.1 Output Connections
        2. 2.1.5.2 Header Information
        3. 2.1.5.3 Default Configuration
        4. 2.1.5.4 How to Generate SYSREF
        5. 2.1.5.5 Multiplier Mode Example
        6. 2.1.5.6 Divider Mode Example
        7. 2.1.5.7 Hybrid Mode: SPI and Pin Mode
  8. 3Software
    1. 3.1 Software Installation
    2. 3.2 Software Description
    3. 3.3 USB2ANY Interface
  9. 4Implementation Results
    1. 4.1 Buffer, Divider, and Multiplier Modes
    2. 4.2 SYSREF Generation
    3. 4.3 SYSREF Delay Generators
  10. 5Hardware Design Files
    1. 5.1 Schematic
    2. 5.2 PCB Layout
      1. 5.2.1 PCB Layer Stack-Up
    3. 5.3 Bill of Materials
  11. 6Additional Information
    1. 6.1 Troubleshooting Guide
      1. 6.1.1 General Guidance
      2. 6.1.2 If Output Is Not Seen on CLKOUT
      3. 6.1.3 If Device Features Are Not Active
      4. 6.1.4 If Multiplier Frequency Is Not Accurate
      5. 6.1.5 If Divider Frequency Is Not Accurate
      6. 6.1.6 If SYSREF Is Not Observed
    2. 6.2 Trademarks

6.1.6 If SYSREF Is Not Observed

There are several settings which must be correct to achieve SYSREF outputs.

  • Make sure of the following settings:
    • Set SYSREF_MODE to Continuous (for debugging).
    • SRREQ_MODE field set to SYSREFREQ mode.
    • SRREQ_VCM set for DC-coupled, with about 1.1 V on SYSREFREQ_P and 1.5 V on SYSREFREQ_N.
    • SYSREF_DLY_BYP field set to use delay.
    • SYSREF_EN=1.
  • Make sure the frequencies of the SYSREF_DLY_DIV, SYSREF_DIV_PRE, and SYSREF_DLY_ADJ are correctly configured. The GUI highlights any frequency violations.
  • Make sure that FINTERPOLATOR % FSYSREF = 0. The GUI highlights the SYSREF divider in case of violations.
  • Make sure that the output channel (CHx_EN/LOGIC_EN) and the SYSREF buffer (SYSOUTx_EN / LOGISYS_EN) are enabled.
  • Confirm that Windowing mode is not enabled on the User Controls page (SYSWND_EN=0).
  • Confirm that R15[9]=1. This is set automatically by the GUI, so this potential root cause is rare.
  • Confirm the 1.1-V and 1.5-V source for SYSREFREQ_N and SYSREFREQ_P respectively are actually resulting in the required voltages at the pins. If power supplies are used for these voltages, then for the supplies to be unable to sink current is uncommon. The 1.1-V source is not able to sink current from the 1.5-V supply through the internal 100-Ω impedance. An arbitrary function generator is recommended if possible.