SNAU288 December   2023 LMX1906-SP

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Setup
      1. 2.1.1 Evaluation Setup Requirement
      2. 2.1.2 Connection Diagram
        1. 2.1.2.1 How to Enable Full SPI Control
      3. 2.1.3 Power Requirements
      4. 2.1.4 Pin Mode Strapping
      5. 2.1.5 Reference Clock
        1. 2.1.5.1 Output Connections
        2. 2.1.5.2 Header Information
        3. 2.1.5.3 Default Configuration
        4. 2.1.5.4 How to Generate SYSREF
        5. 2.1.5.5 Multiplier Mode Example
        6. 2.1.5.6 Divider Mode Example
        7. 2.1.5.7 Hybrid Mode: SPI and Pin Mode
  8. 3Software
    1. 3.1 Software Installation
    2. 3.2 Software Description
    3. 3.3 USB2ANY Interface
  9. 4Implementation Results
    1. 4.1 Buffer, Divider, and Multiplier Modes
    2. 4.2 SYSREF Generation
    3. 4.3 SYSREF Delay Generators
  10. 5Hardware Design Files
    1. 5.1 Schematic
    2. 5.2 PCB Layout
      1. 5.2.1 PCB Layer Stack-Up
    3. 5.3 Bill of Materials
  11. 6Additional Information
    1. 6.1 Troubleshooting Guide
      1. 6.1.1 General Guidance
      2. 6.1.2 If Output Is Not Seen on CLKOUT
      3. 6.1.3 If Device Features Are Not Active
      4. 6.1.4 If Multiplier Frequency Is Not Accurate
      5. 6.1.5 If Divider Frequency Is Not Accurate
      6. 6.1.6 If SYSREF Is Not Observed
    2. 6.2 Trademarks

4.1 Buffer, Divider, and Multiplier Modes

From the top-menu, click Default Configuration → 800 MHz Buffer Mode. This automatically loads the buffer mode profile.

GUID-1292A9AD-8AE8-46F5-B037-C34B1701791A-low.pngFigure 4-1 Loading the Default Configuration

If termination is not applied on all output pins, then manually disable the unused outputs using the CHx_EN fields (to completely power down unused channels) or the CLKOUTx_EN, SYSOUTx_EN, and LOGICLK_EN/LOGISYS_EN fields (to power down output buffers only). Powering down unused channels greatly reduces current consumption, and for the logic clocks in particular can reduce spurious interference.

After the profile is loaded and required any changes have been made, the signal analyzer shows an 800-MHz signal at around +6-dBm single-ended, or +9-dBm differential.

The blue trace is the reference clock from SMA100B and the yellow trace is the 800 MHz buffered output.

GUID-20231114-SS0I-KBZF-LPLN-S8N1ZS5KKWJJ-low.pngFigure 4-2 800-MHz Buffer Mode Signal Analyzer Plot

To activate the multiplier or the divider, change the CLK_MUX field to specify divider or multiplier modes, and change the CLK_DIV and CLK_MULT fields to specify the frequency scaling factor. To make sure the device cleanly enters each mode, first, the desired configuration must be prepared in the GUI. Then, from the User Controls page the device must be reset by toggling the RESET field, and finally the registers must be reloaded using the USB Communications → Write All Registers menu option, or by pressing the accelerator keys CTRL + L.

The yellow trace is the 400 MHz divided output.

GUID-20231114-SS0I-GRR5-HL4Z-PXTWN42BMHB3-low.pngFigure 4-3 800-MHz Divide-by-2 Mode Signal Analyzer Plot

The yellow trace is the 3200 MHz output.

GUID-20231114-SS0I-0JCD-QZGS-CZ56FVMDZRG4-low.pngFigure 4-4 800-MHz Multiplier x4 Mode Signal Analyzer Plot