SNAU288 December   2023 LMX1906-SP

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Setup
      1. 2.1.1 Evaluation Setup Requirement
      2. 2.1.2 Connection Diagram
        1. 2.1.2.1 How to Enable Full SPI Control
      3. 2.1.3 Power Requirements
      4. 2.1.4 Pin Mode Strapping
      5. 2.1.5 Reference Clock
        1. 2.1.5.1 Output Connections
        2. 2.1.5.2 Header Information
        3. 2.1.5.3 Default Configuration
        4. 2.1.5.4 How to Generate SYSREF
        5. 2.1.5.5 Multiplier Mode Example
        6. 2.1.5.6 Divider Mode Example
        7. 2.1.5.7 Hybrid Mode: SPI and Pin Mode
  8. 3Software
    1. 3.1 Software Installation
    2. 3.2 Software Description
    3. 3.3 USB2ANY Interface
  9. 4Implementation Results
    1. 4.1 Buffer, Divider, and Multiplier Modes
    2. 4.2 SYSREF Generation
    3. 4.3 SYSREF Delay Generators
  10. 5Hardware Design Files
    1. 5.1 Schematic
    2. 5.2 PCB Layout
      1. 5.2.1 PCB Layer Stack-Up
    3. 5.3 Bill of Materials
  11. 6Additional Information
    1. 6.1 Troubleshooting Guide
      1. 6.1.1 General Guidance
      2. 6.1.2 If Output Is Not Seen on CLKOUT
      3. 6.1.3 If Device Features Are Not Active
      4. 6.1.4 If Multiplier Frequency Is Not Accurate
      5. 6.1.5 If Divider Frequency Is Not Accurate
      6. 6.1.6 If SYSREF Is Not Observed
    2. 6.2 Trademarks

2.1.2 Connection Diagram

GUID-20231027-SS0I-WS0G-21ZN-SVLFTT7TB1LC-low.svg Figure 2-1 EVM Connection Diagram
Table 2-1 SPI Test Points
Test Point Net
TP1 SDO
TP4 CSB
TP5 SCK
TP6 SDI
TP9 CE
Table 2-2 I2C Testpoints for IO Expander
Test Point Net
TP10 SDA
TP11 SCL
Table 2-3 Supply Voltage Test Points
Test Point Net
TP7 VCC01_23
TP12 VCC_CLK_LOGIC
TP14 VCC_PinM
TP16 VCC_BIAS
Table 2-4 VCC Power Jumpers
Header Net Short Position Configuration

J14

CE

1-2 (EVM default)

CE pulled high via 10 kΩ resistor results in LMX1909-SP enabled

2-3

External CE signal from USB2ANY in TICSpro 'pin' tab
J28 VCC_BYPASS or 1st LDO

2-3 (EVM default)

Use on-board LDOS

1-2

Direct Supply from J23 (VCCIN) SMA connector
J29 VCC_IN or VCC_BYPASS 2-3 (EVM default) Use on-board LDOS

1-2

 Direct Supply from J23 (VCCIN) SMA connector
J40 VCC_IN or 2nd LDO 2-3 (EVM default) Use on-board LDOS
1-2 Direct Supply from J23 (VCCIN) SMA connector
Table 2-5 Pin Control Jumpers (IO Expander Configurable)
Jumper Short position Configuration

SYSREFEN (Acts as CE pin for entire SYSREF sub-system)

J38-J39 (Pulled HIGH)

When SYSREFEN is set to HIGH, the entire SYSREF sub-system is enabled with register defaults set accordingly. SPI can still be used to disable.

J37-J38 (Pulled LOW)

When SYSREFEN is set to low, the entire SYSREF sub-system is deactivated and SPI cannot re-enable.

LOGICEN (Acts as CE pin for LOGICH)

J38-J39 (Pulled HIGH)

 When LOGICEN is set to HIGH, the entire SYSREF sub-system is enabled with register defaults set accordingly. SPI can still be used to disable.
J37-J38 (Pulled LOW) When LOGICEN is set to low, all FPGA/LOGIC circuits and the SYSREF sub-system are deactivated and SPI cannot re-enable.
Table 2-6 Pin State Headers (IO Expander Configurable)
Header Short Position Configuration
PWRSEL[2:0] 000 Output power configurable via SPI
001 - Lowest output power Pin Mode (Also controllable via IO expander)
⋮
111 - Highest Output Power
CLKx_EN Pulled LOW (GND) J31-J32 Disables corresponding CLKOUTx
Pulled HIGH (VCC) J32-J33 Enables corresponding CLKOUTx
CAL Transition from LOW to HIGH Calibrates the multiplier or Resets the divider
LOW Calibration & Reset controllable via SPI
WARNING: If the user wishes to use IO expander, then make sure that no shorts are present on any of the header pins. Otherwise, the IO expander or the MCU is damaged.

The onboard TCA9535 IO expander allows the user to change pin states without the need of physical shorts on the header pin. This allows users to toggle pin modes through the GUI as well. If the user wishes to evaluate the LMX1906-SP without MCU control (physical pin strapping), then make sure no jumpers are present on any of the pin state headers.

USB POWER needs to be provided if LDOs utilization is desired. VCCIN can have a 3.3 V supply connected but, if the USB cable is disconnected, then the board is without power.

Table 2-7 Usage Modes
Usage Configuration
With USB & DUT LDOs
  • Short J28, J29 and J40 jumpers to LDO
  • Apply 3.3 V to VCCIN
  • Apply USB connection
Without USB & DUT LDOs
  • Short J28, J29 and J40 jumpers to LDO
  • Apply 3.3 V to VCCIN
  • Apply 5 V to VBIAS (TP16) - To avoid damage to host pc usb port, do not apply external source to vbias unless usb is disconnected or r44 has been removed.
With USB & DUT LDOs bypassed
  • Short J28, J29 and J40 jumpers to bypass
  • Apply 2.5 V to VCCIN
  • Apply USB connection
Without USB & DUT LDOs bypassed
  • Short J28, J29 and J40 jumpers to LDO
  • Apply 2.5 V to VCCIN
Note: SPI reading while using DUT LDOs: 3.3 V supply can prevent SPI read-back from functioning as intended. Make sure the input voltage to U7 is larger than 0.7 * VCCIN and that output voltage of U7 is greater than 2.31 V.