SNAU303A May   2024  – September 2024

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
  7. 2Hardware
    1. 2.1 Setup
      1. 2.1.1 Default Configuration of the LMH1239EVM
      2. 2.1.2 Hardware and Software: Description and Setup
        1. 2.1.2.1 SDI_IN1 Selected
        2. 2.1.2.2 SMBus/I2C Secondary Mode Configuration for the LMH1239EVM GUI
        3. 2.1.2.3 High Level Page for the LMH1239EVM GUI
        4. 2.1.2.4 Eye Monitor for the LMH1239EVM GUI
          1. 2.1.2.4.1 Register Map for the LMH1239EVM GUI
        5. 2.1.2.5 Scripting for the LMH1239EVM GUI
  8. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layout
    3. 3.3 Bill of Materials (BOM)
  9. 4Additional Information
    1. 4.1 Trademarks
  10. 5Related Documentation
  11. 6Revision History

2.1 Setup

The LMH1239EVM can be used in one of three modes:

  1. Pin Mode (Default) – Provides general access to the LMH1239 signal integrity and I/O control settings with IC pin-level logic.
  2. SPI Mode – Provides full access to the LMH1239 signal integrity and control settings through the POCI, PICO, SCK, and CS pins.
  3. SMBus Mode – Provides full access to the LMH1239 signal integrity and control settings through the SDA, SCL, and GND pins. ADDR0 and ADDR1 pins are used for SMBus address strap.

Using either SPI or SMBus mode, users have full access to all register controls in the LMH1239. For convenience, the LMH1239EVM features an on-chip MSP430 that is configured as a USB2ANY interface between the LMH1239 and PC through the mini-USB port header on J31.

Note:

Currently, the interface from the PC to the onboard MSP430 can only support SMBus communication.

The external control pins on the LMH1239EVM are used to configure the default device settings. A 4-level input scheme across the control pin interface increases the amount of control levels available to the device with fewer physical pins. The channel settings and controls are configurable in pin mode for the LMH1239 4-logic levels (L, R, F, H). The four logic levels correspond to the following voltages in Table 2-1.

Table 2-1 Description of 4-Level Voltage Inputs and Jumper Ties
LEVELSETTINGNOMINAL PIN VOLTAGE
HTie 1kΩ to VINVIN
FFloat (leave pin open)2/3 × VIN
RTie 20kΩ to GND1/3 × VIN
LTie 1kΩ to GND0

Typical 4-level input thresholds:

  • Internal threshold between L and R = 0.2 × VIN
  • Internal threshold between R and F = 0.5 × VIN
  • Internal threshold between F and H = 0.8 × VIN

To set these 4-level voltage inputs, each input is controlled by a group of 6 jumper pins set in Figure 2-1.

LMH1239EVM Jumper Orientation for User ConfigurationFigure 2-1 Jumper Orientation for User Configuration

Therefore, the following jumper positions allow access to each of the four logic levels:

LEVELJUMPER TIES
HPin 1-3
FPin 3-4 (or no connect)
RPin 4-6
LPin 3-5

The following jumpers have 4-level input control: J10, J11, J12, J13, J14, J15, J16, J17, J18, and J19.

In Pin Mode, the OUT0_OUT1_SEL, LOOP_BW_SEL, VOD_DEM_SEL, MODE_SEL, OUT_CTRL, SDI_VOD, SDI_OUT_ENA and SDI_IN_SEL pins control different LMH1239 settings. Using SPI or SMBus, these initial pin control values can be overridden by setting the appropriate override bits through register control. Both SPI and SMBus interfaces allow full control over a wide range of device settings. See Table 2-2 and Table 2-3 for jumper descriptions and differences.

Table 2-2 Description of Connections in SPI Mode (MODE_SEL = Level F)
COMPONENTNAMECOMMENTS
J1GNDGND power supply
J2VIN2.5 V VIN power supply
J5ENABLEEnable pin for the LMH1239. Shunt Pin 1 and 2 for proper operation. Refer to LMH1239 data sheet for detailed information.
J6POCIShunt Pin 1 and 2 to connect POCI signal to J8 for proper SPI mode operation.
J7LOCK_NReclocker lock indicator for the selected input. Shunt Pin 1 and 2 for proper operation. Refer to LMH1239 data sheet for detailed controls.
J8SPI AccessSPI access pins. See data sheet and EVM schematic for detailed pin-out information.
J9SPI Access

For SPI mode, install pin 1-2, 3-4, and 5-6 for SPI 3.3 V to 2.5 V level shift. Leave pin 7-10 open.

See data sheet for additional information on SPI operation.

J10OUT0_OUT1_SEL

OUT0_OUT1_SEL pin selects the SMA outputs.

H: OUT0 and OUT1 muted.

F and L: OUT0 enabled and OUT1 muted.

R: OUT0 and OUT1 enabled.

J11LOOP­_BW_SEL

LOOP­_BW_SEL-

H: 13 MHz/7 MHz/5 MHz/3 MHz/1 MHz.

F: 13 MHz/7 MHz/5 MHz/3 MHz/1 MHz.

R: 800 KHz/437 KHz/312 KHz/187 KHz/62 KHz.

L: 400 KHz/219 KHz/156 KHz/94 KHz/31 KHz.

Note: These are for 12 Gbps/6 Gbps/3 Gbps/HD/SD data rates. External caps are needed for H, R and L cases.
J12VOD_DEM_SEL

VOD_DEM_SEL-

H:410 mVpp, 0dB DEM

F:560 mVpp, -0.9dB

R: 635 mVpp, -2.4dB

L: 810 mVpp, -4.0dB

See data sheet and EVM schematic for additional operation information.

J13MODE_SELLevel F: SPI Mode
J14OUT_CTRL

OUT_CTRL selects the signal flow from the selected IN port to the enabled outputs. OUT_CTRL selects reclocked data, reclocked data and clock, bypass reclocker (equalized data route to output driver), or both equalizer and reclocker bypassed.

J15SDI_VOD

SDI VOD -

H: About +5% (nominal)

F: 800 mVpp (nominal)

R: About 10% of nominal

L: About -5% of nominal

J16CS_N_ADDR0Chip select. When CS_N is at logic low, CS_N enables SPI access to the LMH1239 peripheral device.
J17POCI_ADDR1

POCI is the SPI serial control data output from the LMH1239 peripheral device.

POCI is a 2.5V LVCMOS output.

J18SDI_OUT_ENA

SDI_OUT_ENA pin enables or disables the SDI_OUT 75Ω output.

H: SDI_OUT Disabled

F and R: Do not use

L: SDI_OUT Enabled

See data sheet and EVM schematic for additional operation information.

J19SDI_IN_SELSDI_IN_SEL pin determines the SDI-IN 75Ω input that is enabled. Level F: SDI-IN0. See data sheet and EVM schematic for additional operation information.
Table 2-3 Description of Connections in SMBus Mode (MODE_SEL = Level L)
COMPONENTNAMECOMMENTS
J6POCILeave Pin 1 and 2 open for proper SMBus operation.
J7LOCK_NReclocker lock indicator for the selected input. Shunt Pin 1 and 2 for proper operation. Refer to the LMH1239 data sheet for detailed controls.
J8SMBus AccessSMBus access pins. See the data sheet and EVM schematic for detailed pinout information.
J9SMBus AccessExternal 2kΩ pullup resistor to 3.3 V supply. Install shunt jumpers on pins 7-8 and 9-10 for proper operation. Leave pins 1-6 open. See the data sheet for additional information on SMBus operation.
J13MODE_SELLevel L: SMBus mode.
J16ADDR04-Level strap pins to determine up to 16 unique SMBus address with J17 to create AD[1:0].
J17ADDR14-Level strap pins to determine up to 16 unique SMBus address with J16 to create AD[1:0]. See Table 2-5 for different SMBus address combinations.
Table 2-4 Input and Output Channel Connections
SIGNAL INPUTS AND OUTPUTS
JUNCTION NUMBERSFUNCTION
J4, J32SDI_OUT+, SDI_OUT- (BNC single-ended)
J22, J3SDI_IN+, SDI_IN1+ (BNC single-ended)
J22, J23OUT0+, OUT0– (SMA)
J24, J25OUT1+, OUT1– (SMA)
Note: Jumpers not listed in Table 2-3 are identical to the functions mentioned in Table 2-2.