The logic input and output
pins on LMKDB1204 provides option for selecting different device
modes, input clock selection, output enable / disable control, loss
of signal (LOS) detection, and output impedance selection. The
following section describes the function of different input and
output logic pins. Voltage levels for input pins can be set through
TICSPro GUI using the MSP430 MCU or using on-board jumper as
specified in Table 4-1.
Table 3-3 Device
Start-Up Modes
SMB_EN INPUT
LEVEL |
START-UP
MODE |
Low (default) |
SMBus inactive. |
High |
SMBus active. On-board jumper headers on
JP4 and JP5 need to be removed for proper
operation. |
Table 3-4 Clock Input Selection
CLKIN_SEL_tri Output Level |
Function |
Low |
CLKIN0 is
the input source for all outputs. |
High |
CLKIN1 is
the input source for all outputs. |
Hi-Z |
CLKIN0 is
the input source for BANK0 outputs and CLKIN1 is
the input source for BANK1 outputs. JP4 must be
removed and R51 must be depopulated. If
SMBus mode needs to be activated after
removing R51, then on-board header jumper
JP4 needs to be set to high. |
Table 3-5 Output Enable
Pin Control
OE0# to OE3#
INPUT LEVEL |
OUTPUT
STATUS |
Low (default) |
Enabled. |
High |
Disabled |
Note: For OE3#, when controlling the pin by only using
the on-board jumper header on JP5 (and not the MSP430 MCU) and SMBus
is disabled/SMB_EN = high, thenR52 must be depopulated. If
SMBus mode needs to be activated after removing R52,
then on-board header jumper on JP5 needs to be set to high.
Table 3-6 Loss of Signal
(LOS) Detection (Status pin)
LOSb OUTPUT
LEVEL |
LOS
STATUS |
Low |
Not detected |
High |
Detected |
Table 3-7 LP-HCSL
Differential CLock Output Impedance Select
ZOUT_SEL Output Level |
Function |
Low |
LMKDB1204 has 85Ω output
termination. |
High |
LMKDB1204 has 100Ω output
termination. |