SNLA132G October   2011  – November 2020 DS90UB928Q-Q1 , DS90UB941AS-Q1 , DS90UB948-Q1 , DS90UH925Q-Q1 , DS90UH926Q-Q1 , DS90UH940N-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Overview of Internal Test Pattern Generation
    1. 2.1 Color Mode
    2. 2.2 Video Timing Modes
    3. 2.3 Clock Generation
    4. 2.4 Pattern Selection
    5. 2.5 Pattern Inversion
    6. 2.6 Auto-Scrolling
  4. 3Serial Control Bus Registers for Internal Test Pattern Generation
    1. 3.1 Direct Register Map
      1. 3.1.1 Control and Configuration
      2. 3.1.2 Indirect Access Address and Data
      3. 3.1.3 DS90Ux928Q-Q1/DS90UB924-Q1 Internal Clock Source
    2. 3.2 Indirect Register Map
      1. 3.2.1 General Control
      2. 3.2.2 Internal Timing Control
      3. 3.2.3 Auto-Scrolling Control
  5. 4Configuration Examples
    1. 4.1 Auto-Scrolling Configuration
    2. 4.2 Internal Default Timing Configuration
    3. 4.3 Custom Display Configuration
    4. 4.4 1080p60 with External Clock Example Configuration
    5. 4.5 Resolution Readback Example
  6. 5Conclusion
  7. 6References
  8. 7Revision History

3.1.2 Indirect Access Address and Data

The PGIA and PGID registers are used to indirectly access the detailed configuration registers for the Internal Test Pattern Generator. To use these registers to access the indirect register space, perform the following steps:

  • Set PGIA to the indirect register address to be read/written.
  • To READ indirect register: Read from PGID.
  • To WRITE indirect register: Write indirect register data to PGID.
    Table 3-2 Pattern Generator Indirect Registers
    ADD(hex)Register NameBitAccessDefault (hex)FunctionDescription
    0x66Pattern Generator Indirect Address
    (PGIA)    		7:0RW0x00Indirect AddressThis 8-bit field sets the indirect address for accesses to indirectly-mapped registers. It should be written prior to reading or writing the Pattern Generator Indirect Data Register (PGID).
    0x67Pattern Generator Indirect Data
    (PGID)    		7:0RW0x00Indirect DataWhen writing to indirect registers, this register contains the data to be written. When reading from indirect registers, this register contains the read back value.