SNLA132G October   2011  – November 2020 DS90UB928Q-Q1 , DS90UB941AS-Q1 , DS90UB948-Q1 , DS90UH925Q-Q1 , DS90UH926Q-Q1 , DS90UH940N-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Overview of Internal Test Pattern Generation
    1. 2.1 Color Mode
    2. 2.2 Video Timing Modes
    3. 2.3 Clock Generation
    4. 2.4 Pattern Selection
    5. 2.5 Pattern Inversion
    6. 2.6 Auto-Scrolling
  4. 3Serial Control Bus Registers for Internal Test Pattern Generation
    1. 3.1 Direct Register Map
      1. 3.1.1 Control and Configuration
      2. 3.1.2 Indirect Access Address and Data
      3. 3.1.3 DS90Ux928Q-Q1/DS90UB924-Q1 Internal Clock Source
    2. 3.2 Indirect Register Map
      1. 3.2.1 General Control
      2. 3.2.2 Internal Timing Control
      3. 3.2.3 Auto-Scrolling Control
  5. 4Configuration Examples
    1. 4.1 Auto-Scrolling Configuration
    2. 4.2 Internal Default Timing Configuration
    3. 4.3 Custom Display Configuration
    4. 4.4 1080p60 with External Clock Example Configuration
    5. 4.5 Resolution Readback Example
  6. 5Conclusion
  7. 6References
  8. 7Revision History

2 Overview of Internal Test Pattern Generation

The internal test patterns are simple and repetitive in order to allow quick visual verification of system and display panel operation. As long as the device is not in power down mode, a test pattern can be generated, even if the device is not linked to a source. If no clock is received, the test pattern can be configured to use an internally generated programmable pixel clock.

Video timing may be based on external control signals (HS, VS, DE) provided at the serializer inputs, or they may be generated internally by either the serializer or the deserializer (Figure 2-1).

GUID-6F53FAEC-E959-4BC1-8FA8-3EE3B57C62E3-low.gif Figure 2-1 Configuration Options

No pin configuration is required to enable or control the pattern generation feature. All aspects of pattern generation are controlled through the device control registers, accessible locally through the device I2C interface, or remotely via the FPD-Link III bidirectional control channel. The test pattern generation feature is able to handle a wide range of display timings and test image options:

  • Five pre-configured solid color outputs
  • One user-configurable solid color output
  • Horizontal ramp over full dynamic range of red, green, blue, or white
  • Vertical ramp over full dynamic range of red, green, blue, or white
  • Automatic scaling of brightness ramps based on frame size
  • VCOM, Checkerboard, and Color Bars patterns (For all devices listed in Table 1-1 except DS90UB921-Q1, DS90Ux925Q-Q1, and DS90Ux926Q-Q1)
  • Optional color inversion
  • Flexible Auto-scrolling mechanism that rotates through a user-defined list of patterns
  • Fully programmable internal video clock and timing generation
  • Optional 18-bit color mode